xref: /rk3399_ARM-atf/plat/rockchip/common/bl31_plat_setup.c (revision 394fa5d499fdfc1a0ddcaa3f2640cf5c49c25b63)
1 /*
2  * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <platform_def.h>
10 
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/console.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <drivers/ti/uart/uart_16550.h>
16 #include <lib/coreboot.h>
17 #include <lib/mmio.h>
18 #include <plat_private.h>
19 #include <plat/common/platform.h>
20 
21 static entry_point_info_t bl32_ep_info;
22 static entry_point_info_t bl33_ep_info;
23 
24 /*******************************************************************************
25  * Return a pointer to the 'entry_point_info' structure of the next image for
26  * the security state specified. BL33 corresponds to the non-secure image type
27  * while BL32 corresponds to the secure image type. A NULL pointer is returned
28  * if the image does not exist.
29  ******************************************************************************/
30 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
31 {
32 	entry_point_info_t *next_image_info;
33 
34 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
35 
36 	/* None of the images on this platform can have 0x0 as the entrypoint */
37 	if (next_image_info->pc)
38 		return next_image_info;
39 	else
40 		return NULL;
41 }
42 
43 #pragma weak params_early_setup
44 void params_early_setup(void *plat_param_from_bl2)
45 {
46 }
47 
48 /*******************************************************************************
49  * Perform any BL3-1 early platform setup. Here is an opportunity to copy
50  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
51  * are lost (potentially). This needs to be done before the MMU is initialized
52  * so that the memory layout can be used while creating page tables.
53  * BL2 has flushed this information to memory, so we are guaranteed to pick up
54  * good data.
55  ******************************************************************************/
56 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
57 				u_register_t arg2, u_register_t arg3)
58 {
59 	static console_16550_t console;
60 	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
61 	void *plat_params_from_bl2 = (void *) arg1;
62 
63 	params_early_setup(plat_params_from_bl2);
64 
65 #if COREBOOT
66 	if (coreboot_serial.type)
67 		console_16550_register(coreboot_serial.baseaddr,
68 				       coreboot_serial.input_hertz,
69 				       coreboot_serial.baud,
70 				       &console);
71 #else
72 	console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
73 			       PLAT_RK_UART_BAUDRATE, &console);
74 #endif
75 
76 	VERBOSE("bl31_setup\n");
77 
78 	/* Passing a NULL context is a critical programming error */
79 	assert(arg_from_bl2);
80 
81 	assert(arg_from_bl2->h.type == PARAM_BL31);
82 	assert(arg_from_bl2->h.version >= VERSION_1);
83 
84 	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
85 	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
86 }
87 
88 /*******************************************************************************
89  * Perform any BL3-1 platform setup code
90  ******************************************************************************/
91 void bl31_platform_setup(void)
92 {
93 	generic_delay_timer_init();
94 	plat_rockchip_soc_init();
95 
96 	/* Initialize the gic cpu and distributor interfaces */
97 	plat_rockchip_gic_driver_init();
98 	plat_rockchip_gic_init();
99 	plat_rockchip_pmu_init();
100 }
101 
102 /*******************************************************************************
103  * Perform the very early platform specific architectural setup here. At the
104  * moment this is only intializes the mmu in a quick and dirty way.
105  ******************************************************************************/
106 void bl31_plat_arch_setup(void)
107 {
108 	plat_cci_init();
109 	plat_cci_enable();
110 	plat_configure_mmu_el3(BL_CODE_BASE,
111 			       BL_COHERENT_RAM_END - BL_CODE_BASE,
112 			       BL_CODE_BASE,
113 			       BL_CODE_END,
114 			       BL_COHERENT_RAM_BASE,
115 			       BL_COHERENT_RAM_END);
116 }
117