16fba6e04STony Xie /* 26fba6e04STony Xie * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 46fba6e04STony Xie * Redistribution and use in source and binary forms, with or without 56fba6e04STony Xie * modification, are permitted provided that the following conditions are met: 66fba6e04STony Xie * 76fba6e04STony Xie * Redistributions of source code must retain the above copyright notice, this 86fba6e04STony Xie * list of conditions and the following disclaimer. 96fba6e04STony Xie * 106fba6e04STony Xie * Redistributions in binary form must reproduce the above copyright notice, 116fba6e04STony Xie * this list of conditions and the following disclaimer in the documentation 126fba6e04STony Xie * and/or other materials provided with the distribution. 136fba6e04STony Xie * 146fba6e04STony Xie * Neither the name of ARM nor the names of its contributors may be used 156fba6e04STony Xie * to endorse or promote products derived from this software without specific 166fba6e04STony Xie * prior written permission. 176fba6e04STony Xie * 186fba6e04STony Xie * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 196fba6e04STony Xie * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 206fba6e04STony Xie * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 216fba6e04STony Xie * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 226fba6e04STony Xie * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 236fba6e04STony Xie * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 246fba6e04STony Xie * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 256fba6e04STony Xie * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 266fba6e04STony Xie * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 276fba6e04STony Xie * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 286fba6e04STony Xie * POSSIBILITY OF SUCH DAMAGE. 296fba6e04STony Xie */ 306fba6e04STony Xie 316fba6e04STony Xie #include <arm_gic.h> 326fba6e04STony Xie #include <assert.h> 336fba6e04STony Xie #include <bl_common.h> 346fba6e04STony Xie #include <console.h> 356fba6e04STony Xie #include <debug.h> 366704f425SAntonio Nino Diaz #include <generic_delay_timer.h> 376fba6e04STony Xie #include <mmio.h> 386fba6e04STony Xie #include <platform.h> 396fba6e04STony Xie #include <plat_private.h> 406fba6e04STony Xie #include <platform_def.h> 416fba6e04STony Xie 426fba6e04STony Xie /******************************************************************************* 436fba6e04STony Xie * Declarations of linker defined symbols which will help us find the layout 446fba6e04STony Xie * of trusted SRAM 456fba6e04STony Xie ******************************************************************************/ 466fba6e04STony Xie unsigned long __RO_START__; 476fba6e04STony Xie unsigned long __RO_END__; 486fba6e04STony Xie 496fba6e04STony Xie /* 506fba6e04STony Xie * The next 2 constants identify the extents of the code & RO data region. 516fba6e04STony Xie * These addresses are used by the MMU setup code and therefore they must be 526fba6e04STony Xie * page-aligned. It is the responsibility of the linker script to ensure that 536fba6e04STony Xie * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 546fba6e04STony Xie */ 556fba6e04STony Xie #define BL31_RO_BASE (unsigned long)(&__RO_START__) 566fba6e04STony Xie #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 576fba6e04STony Xie 586fba6e04STony Xie static entry_point_info_t bl32_ep_info; 596fba6e04STony Xie static entry_point_info_t bl33_ep_info; 606fba6e04STony Xie 616fba6e04STony Xie /******************************************************************************* 626fba6e04STony Xie * Return a pointer to the 'entry_point_info' structure of the next image for 636fba6e04STony Xie * the security state specified. BL33 corresponds to the non-secure image type 646fba6e04STony Xie * while BL32 corresponds to the secure image type. A NULL pointer is returned 656fba6e04STony Xie * if the image does not exist. 666fba6e04STony Xie ******************************************************************************/ 676fba6e04STony Xie entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 686fba6e04STony Xie { 696fba6e04STony Xie entry_point_info_t *next_image_info; 706fba6e04STony Xie 716fba6e04STony Xie next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 726fba6e04STony Xie 736fba6e04STony Xie /* None of the images on this platform can have 0x0 as the entrypoint */ 746fba6e04STony Xie if (next_image_info->pc) 756fba6e04STony Xie return next_image_info; 766fba6e04STony Xie else 776fba6e04STony Xie return NULL; 786fba6e04STony Xie } 796fba6e04STony Xie 806fba6e04STony Xie /******************************************************************************* 816fba6e04STony Xie * Perform any BL3-1 early platform setup. Here is an opportunity to copy 826fba6e04STony Xie * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 836fba6e04STony Xie * are lost (potentially). This needs to be done before the MMU is initialized 846fba6e04STony Xie * so that the memory layout can be used while creating page tables. 856fba6e04STony Xie * BL2 has flushed this information to memory, so we are guaranteed to pick up 866fba6e04STony Xie * good data. 876fba6e04STony Xie ******************************************************************************/ 886fba6e04STony Xie void bl31_early_platform_setup(bl31_params_t *from_bl2, 896fba6e04STony Xie void *plat_params_from_bl2) 906fba6e04STony Xie { 916fba6e04STony Xie console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 926fba6e04STony Xie PLAT_RK_UART_BAUDRATE); 936fba6e04STony Xie 946fba6e04STony Xie VERBOSE("bl31_setup\n"); 956fba6e04STony Xie 966fba6e04STony Xie /* Passing a NULL context is a critical programming error */ 976fba6e04STony Xie assert(from_bl2); 986fba6e04STony Xie 996fba6e04STony Xie assert(from_bl2->h.type == PARAM_BL31); 1006fba6e04STony Xie assert(from_bl2->h.version >= VERSION_1); 1016fba6e04STony Xie 1026fba6e04STony Xie bl32_ep_info = *from_bl2->bl32_ep_info; 1036fba6e04STony Xie bl33_ep_info = *from_bl2->bl33_ep_info; 1046fba6e04STony Xie 1056fba6e04STony Xie plat_rockchip_pmusram_prepare(); 10668ff45f4SCaesar Wang 10768ff45f4SCaesar Wang /* there may have some board sepcific message need to initialize */ 10868ff45f4SCaesar Wang params_early_setup(plat_params_from_bl2); 1096fba6e04STony Xie } 1106fba6e04STony Xie 1116fba6e04STony Xie /******************************************************************************* 1126fba6e04STony Xie * Perform any BL3-1 platform setup code 1136fba6e04STony Xie ******************************************************************************/ 1146fba6e04STony Xie void bl31_platform_setup(void) 1156fba6e04STony Xie { 1166704f425SAntonio Nino Diaz generic_delay_timer_init(); 1176fba6e04STony Xie plat_rockchip_soc_init(); 1186fba6e04STony Xie 1196fba6e04STony Xie /* Initialize the gic cpu and distributor interfaces */ 1206fba6e04STony Xie plat_rockchip_gic_driver_init(); 1216fba6e04STony Xie plat_rockchip_gic_init(); 1226fba6e04STony Xie plat_rockchip_pmu_init(); 1236fba6e04STony Xie } 1246fba6e04STony Xie 1256fba6e04STony Xie /******************************************************************************* 1266fba6e04STony Xie * Perform the very early platform specific architectural setup here. At the 1276fba6e04STony Xie * moment this is only intializes the mmu in a quick and dirty way. 1286fba6e04STony Xie ******************************************************************************/ 1296fba6e04STony Xie void bl31_plat_arch_setup(void) 1306fba6e04STony Xie { 1316fba6e04STony Xie plat_cci_init(); 1326fba6e04STony Xie plat_cci_enable(); 1336fba6e04STony Xie plat_configure_mmu_el3(BL31_RO_BASE, 134*47497053SMasahiro Yamada BL_COHERENT_RAM_END - BL31_RO_BASE, 1356fba6e04STony Xie BL31_RO_BASE, 1366fba6e04STony Xie BL31_RO_LIMIT, 137*47497053SMasahiro Yamada BL_COHERENT_RAM_BASE, 138*47497053SMasahiro Yamada BL_COHERENT_RAM_END); 1396fba6e04STony Xie } 140