1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/cci.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include <plat_private.h> 19 20 #ifdef PLAT_RK_CCI_BASE 21 static const int cci_map[] = { 22 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX, 23 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 24 }; 25 #endif 26 27 /****************************************************************************** 28 * Macro generating the code for the function setting up the pagetables as per 29 * the platform memory map & initialize the mmu, for the given exception level 30 ******************************************************************************/ 31 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 32 void plat_configure_mmu_el ## _el(unsigned long total_base, \ 33 unsigned long total_size, \ 34 unsigned long ro_start, \ 35 unsigned long ro_limit, \ 36 unsigned long coh_start, \ 37 unsigned long coh_limit) \ 38 { \ 39 mmap_add_region(total_base, total_base, \ 40 total_size, \ 41 MT_MEMORY | MT_RW | MT_SECURE); \ 42 mmap_add_region(ro_start, ro_start, \ 43 ro_limit - ro_start, \ 44 MT_MEMORY | MT_RO | MT_SECURE); \ 45 mmap_add_region(coh_start, coh_start, \ 46 coh_limit - coh_start, \ 47 MT_DEVICE | MT_RW | MT_SECURE); \ 48 mmap_add(plat_rk_mmap); \ 49 rockchip_plat_mmu_el##_el(); \ 50 init_xlat_tables(); \ 51 \ 52 enable_mmu_el ## _el(0); \ 53 } 54 55 /* Define EL3 variants of the function initialising the MMU */ 56 DEFINE_CONFIGURE_MMU_EL(3) 57 58 unsigned int plat_get_syscnt_freq2(void) 59 { 60 return SYS_COUNTER_FREQ_IN_TICKS; 61 } 62 63 void plat_cci_init(void) 64 { 65 #ifdef PLAT_RK_CCI_BASE 66 /* Initialize CCI driver */ 67 cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 68 #endif 69 } 70 71 void plat_cci_enable(void) 72 { 73 /* 74 * Enable CCI coherency for this cluster. 75 * No need for locks as no other cpu is active at the moment. 76 */ 77 #ifdef PLAT_RK_CCI_BASE 78 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 79 #endif 80 } 81 82 void plat_cci_disable(void) 83 { 84 #ifdef PLAT_RK_CCI_BASE 85 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 86 #endif 87 } 88