1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <bl_common.h> 9 #include <cci.h> 10 #include <debug.h> 11 #include <plat_private.h> 12 #include <platform_def.h> 13 #include <string.h> 14 #include <utils.h> 15 #include <xlat_tables.h> 16 17 #ifdef PLAT_RK_CCI_BASE 18 static const int cci_map[] = { 19 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX, 20 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 21 }; 22 #endif 23 24 /****************************************************************************** 25 * Macro generating the code for the function setting up the pagetables as per 26 * the platform memory map & initialize the mmu, for the given exception level 27 ******************************************************************************/ 28 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 29 void plat_configure_mmu_el ## _el(unsigned long total_base, \ 30 unsigned long total_size, \ 31 unsigned long ro_start, \ 32 unsigned long ro_limit, \ 33 unsigned long coh_start, \ 34 unsigned long coh_limit) \ 35 { \ 36 mmap_add_region(total_base, total_base, \ 37 total_size, \ 38 MT_MEMORY | MT_RW | MT_SECURE); \ 39 mmap_add_region(ro_start, ro_start, \ 40 ro_limit - ro_start, \ 41 MT_MEMORY | MT_RO | MT_SECURE); \ 42 mmap_add_region(coh_start, coh_start, \ 43 coh_limit - coh_start, \ 44 MT_DEVICE | MT_RW | MT_SECURE); \ 45 mmap_add(plat_rk_mmap); \ 46 rockchip_plat_mmu_el##_el(); \ 47 init_xlat_tables(); \ 48 \ 49 enable_mmu_el ## _el(0); \ 50 } 51 52 /* Define EL3 variants of the function initialising the MMU */ 53 DEFINE_CONFIGURE_MMU_EL(3) 54 55 unsigned int plat_get_syscnt_freq2(void) 56 { 57 return SYS_COUNTER_FREQ_IN_TICKS; 58 } 59 60 void plat_cci_init(void) 61 { 62 #ifdef PLAT_RK_CCI_BASE 63 /* Initialize CCI driver */ 64 cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 65 #endif 66 } 67 68 void plat_cci_enable(void) 69 { 70 /* 71 * Enable CCI coherency for this cluster. 72 * No need for locks as no other cpu is active at the moment. 73 */ 74 #ifdef PLAT_RK_CCI_BASE 75 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 76 #endif 77 } 78 79 void plat_cci_disable(void) 80 { 81 #ifdef PLAT_RK_CCI_BASE 82 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 83 #endif 84 } 85