1# 2# Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Cortex A720 is ARMv9.2A and will enable all features we want 8ARM_ARCH_MAJOR := 9 9ARM_ARCH_MINOR := 2 10 11PROGRAMMABLE_RESET_ADDRESS := 0 12COLD_BOOT_SINGLE_CPU := 1 13ARM_CCI_PRODUCT_ID := 500 14TRUSTED_BOARD_BOOT := 1 15RESET_TO_BL31 := 1 16GENERATE_COT := 1 17ENABLE_SVE_FOR_NS := 1 18ENABLE_SVE_FOR_SWD := 0 19MULTI_CONSOLE_API := 1 20INIT_UNUSED_NS_EL2 := 1 21 22ENABLE_FEAT_AMU := 1 23ENABLE_FEAT_AMUv1p1 := 1 24ENABLE_AMU_AUXILIARY_COUNTERS := 1 25 26ENABLE_PAUTH := 1 27CTX_INCLUDE_PAUTH_REGS := 1 28 29CRASH_REPORTING := 1 30HANDLE_EA_EL3_FIRST_NS := 1 31ENABLE_STACK_PROTECTOR := strong 32 33CTX_INCLUDE_AARCH32_REGS := 0 34 35# Process SET_SCMI_PARAM flag 36# 0:Disable(default), 1:Enable 37ifndef SET_SCMI_PARAM 38 SET_SCMI_PARAM := 0 39 $(eval $(call add_define,SET_SCMI_PARAM)) 40else 41 ifeq (${SET_SCMI_PARAM}, 0) 42 $(eval $(call add_define,SET_SCMI_PARAM)) 43 else ifeq (${SET_SCMI_PARAM},1) 44 $(eval $(call add_define,SET_SCMI_PARAM)) 45 else 46 $(error "Error:SET_SCMI_PARAM=${SET_SCMI_PARAM} is not supported.") 47 endif 48endif 49 50ifeq (${SPD},none) 51 SPD_NONE:=1 52 $(eval $(call add_define,SPD_NONE)) 53endif 54 55# LSI setting common define 56RCAR_X5H:=10 57RCAR_AUTO:=99 58$(eval $(call add_define,RCAR_X5H)) 59$(eval $(call add_define,RCAR_AUTO)) 60$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 61 62ifndef LSI 63 $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI") 64else 65 ifeq (${LSI},AUTO) 66 RCAR_LSI:=${RCAR_AUTO} 67 else ifeq (${LSI},X5H) 68 RCAR_LSI:=${RCAR_X5H} 69 else 70 $(error "Error: ${LSI} is not supported.") 71 endif 72 $(eval $(call add_define,RCAR_LSI)) 73endif 74 75# Disable workarounds unnecessary for Cortex-A720AE 76WORKAROUND_CVE_2017_5715 := 0 77WORKAROUND_CVE_2022_23960 := 0 78ERRATA_A720_AE_3699562 := 1 79 80USE_COHERENT_MEM := 0 81HW_ASSISTED_COHERENCY := 1 82 83PLAT_INCLUDES := -Iplat/renesas/rcar_gen5/include \ 84 -Iplat/renesas/rcar_gen5 \ 85 -Iplat/renesas/common/include \ 86 -Idrivers/renesas/common/scif \ 87 -Idrivers/renesas/common/timer \ 88 -Idrivers/renesas/rcar_gen5/pwrc \ 89 -Idrivers/arm/css/scmi \ 90 -Iinclude/drivers 91 92ifneq (${ENABLE_STACK_PROTECTOR},0) 93BL_COMMON_SOURCES += plat/renesas/common/rcar_stack_protector.c 94endif 95 96# R-Car Gen5 platform uses Arm GIC-Fainlight-AE, 97# which is successor of GIC-700 based on GICv4.1 98GIC_ENABLE_V4_EXTN := 1 99GIC_EXT_INTID := 1 100 101# GIC-600 configuration 102GICV3_SUPPORT_GIC600 := 1 103# Include GICv3 driver files 104USE_GIC_DRIVER := 3 105 106BL31_SOURCES += ${RCAR_GIC_SOURCES} \ 107 lib/cpus/aarch64/cortex_a720_ae.S \ 108 plat/common/plat_psci_common.c \ 109 plat/renesas/rcar_gen5/plat_topology.c \ 110 plat/renesas/rcar_gen5/aarch64/plat_helpers.S \ 111 plat/renesas/rcar_gen5/aarch64/platform_common.c \ 112 plat/renesas/rcar_gen5/bl31_plat_setup.c \ 113 plat/renesas/rcar_gen5/plat_pm.c \ 114 plat/renesas/rcar_gen5/plat_pm_scmi.c \ 115 plat/renesas/rcar_gen5/rcar_common.c \ 116 drivers/delay_timer/delay_timer.c \ 117 drivers/delay_timer/generic_delay_timer.c \ 118 drivers/renesas/common/scif/scif-common.c \ 119 drivers/renesas/common/scif/scif_helpers.S \ 120 drivers/renesas/common/timer/timer.c \ 121 drivers/renesas/rcar_gen5/pwrc/pwrc.c \ 122 drivers/renesas/rcar_gen5/scif/scif.c \ 123 drivers/arm/cci/cci.c \ 124 drivers/arm/css/scmi/scmi_common.c \ 125 drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ 126 drivers/arm/css/scmi/scmi_sys_pwr_proto.c 127 128include lib/xlat_tables_v2/xlat_tables.mk 129PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} 130 131# Pointer Authentication sources 132ifeq (${ENABLE_PAUTH}, 1) 133PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c 134endif 135 136# build the layout images for the bootrom and the necessary srecords 137rcar: rcar_srecord 138distclean realclean clean: clean_srecord 139 140# srecords 141SREC_PATH = ${BUILD_PLAT} 142BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf 143 144clean_srecord: 145 @echo "clean bl31 srecs" 146 rm -f ${SREC_PATH}/bl31.srec 147 148.PHONY: rcar_srecord 149rcar_srecord: $(BL31_ELF_SRC) 150 @echo "generating srec: ${SREC_PATH}/bl31.srec" 151 $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec 152 153