1 /* 2 * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <drivers/io/io_driver.h> 20 #include <drivers/io/io_storage.h> 21 #include <lib/mmio.h> 22 #include <lib/xlat_tables/xlat_tables_defs.h> 23 #include <plat/common/platform.h> 24 25 #include "avs_driver.h" 26 #include "boot_init_dram.h" 27 #include "cpg_registers.h" 28 #include "board.h" 29 #include "emmc_def.h" 30 #include "emmc_hal.h" 31 #include "emmc_std.h" 32 33 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 34 #include "iic_dvfs.h" 35 #endif 36 37 #include "io_common.h" 38 #include "io_rcar.h" 39 #include "qos_init.h" 40 #include "rcar_def.h" 41 #include "rcar_private.h" 42 #include "rcar_version.h" 43 #include "rom_api.h" 44 45 #if RCAR_BL2_DCACHE == 1 46 /* 47 * Following symbols are only used during plat_arch_setup() only 48 * when RCAR_BL2_DCACHE is enabled. 49 */ 50 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 51 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 52 53 #if USE_COHERENT_MEM 54 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 55 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 56 #endif 57 58 #endif 59 60 extern void plat_rcar_gic_driver_init(void); 61 extern void plat_rcar_gic_init(void); 62 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 63 extern void bl2_system_cpg_init(void); 64 extern void bl2_secure_setting(void); 65 extern void bl2_cpg_init(void); 66 extern void rcar_io_emmc_setup(void); 67 extern void rcar_io_setup(void); 68 extern void rcar_swdt_release(void); 69 extern void rcar_swdt_init(void); 70 extern void rcar_rpc_init(void); 71 extern void rcar_pfc_init(void); 72 extern void rcar_dma_init(void); 73 74 static void bl2_init_generic_timer(void); 75 76 /* R-Car Gen3 product check */ 77 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 78 #define TARGET_PRODUCT PRR_PRODUCT_H3 79 #define TARGET_NAME "R-Car H3" 80 #elif RCAR_LSI == RCAR_M3 81 #define TARGET_PRODUCT PRR_PRODUCT_M3 82 #define TARGET_NAME "R-Car M3" 83 #elif RCAR_LSI == RCAR_M3N 84 #define TARGET_PRODUCT PRR_PRODUCT_M3N 85 #define TARGET_NAME "R-Car M3N" 86 #elif RCAR_LSI == RCAR_V3M 87 #define TARGET_PRODUCT PRR_PRODUCT_V3M 88 #define TARGET_NAME "R-Car V3M" 89 #elif RCAR_LSI == RCAR_E3 90 #define TARGET_PRODUCT PRR_PRODUCT_E3 91 #define TARGET_NAME "R-Car E3" 92 #elif RCAR_LSI == RCAR_D3 93 #define TARGET_PRODUCT PRR_PRODUCT_D3 94 #define TARGET_NAME "R-Car D3" 95 #elif RCAR_LSI == RCAR_AUTO 96 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 97 #endif 98 99 #if (RCAR_LSI == RCAR_E3) 100 #define GPIO_INDT (GPIO_INDT6) 101 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 102 #else 103 #define GPIO_INDT (GPIO_INDT1) 104 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 105 #endif 106 107 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 108 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 109 assert_bl31_params_do_not_fit_in_shared_memory); 110 111 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 112 113 /* FDT with DRAM configuration */ 114 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 115 static void *fdt = (void *)fdt_blob; 116 117 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 118 char *string) 119 { 120 /* Just need enough space to store 64 bit decimal integer */ 121 char num_buf[20]; 122 int i = 0; 123 unsigned int rem; 124 125 do { 126 rem = unum % radix; 127 if (rem < 0xa) 128 num_buf[i] = '0' + rem; 129 else 130 num_buf[i] = 'a' + (rem - 0xa); 131 i++; 132 unum /= radix; 133 } while (unum > 0U); 134 135 while (--i >= 0) 136 *string++ = num_buf[i]; 137 *string = 0; 138 } 139 140 #if (RCAR_LOSSY_ENABLE == 1) 141 typedef struct bl2_lossy_info { 142 uint32_t magic; 143 uint32_t a0; 144 uint32_t b0; 145 } bl2_lossy_info_t; 146 147 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 148 uint64_t end_addr, uint32_t format, 149 uint32_t enable, int fcnlnode) 150 { 151 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 152 char nodename[40] = { 0 }; 153 int ret, node; 154 155 /* Ignore undefined addresses */ 156 if (start_addr == 0 && end_addr == 0) 157 return; 158 159 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 160 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 161 162 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 163 if (ret < 0) { 164 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 165 panic(); 166 } 167 168 ret = fdt_setprop_string(fdt, node, "compatible", 169 "renesas,lossy-decompression"); 170 if (ret < 0) { 171 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 172 panic(); 173 } 174 175 ret = fdt_appendprop_string(fdt, node, "compatible", 176 "shared-dma-pool"); 177 if (ret < 0) { 178 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 179 panic(); 180 } 181 182 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 183 if (ret < 0) { 184 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 185 panic(); 186 } 187 188 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 189 if (ret < 0) { 190 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 191 panic(); 192 } 193 194 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 195 if (ret < 0) { 196 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 197 panic(); 198 } 199 200 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 201 if (ret < 0) { 202 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 203 panic(); 204 } 205 } 206 207 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 208 uint64_t end_addr, uint32_t format, 209 uint32_t enable, int fcnlnode) 210 { 211 bl2_lossy_info_t info; 212 uint32_t reg; 213 214 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 215 216 reg = format | (start_addr >> 20); 217 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 218 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 219 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 220 221 info.magic = 0x12345678U; 222 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 223 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 224 225 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 226 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 227 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 228 229 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 230 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 231 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 232 } 233 #endif 234 235 void bl2_plat_flush_bl31_params(void) 236 { 237 uint32_t product_cut, product, cut; 238 uint32_t boot_dev, boot_cpu; 239 uint32_t lcs, reg, val; 240 241 reg = mmio_read_32(RCAR_MODEMR); 242 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 243 244 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 245 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 246 emmc_terminate(); 247 248 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 249 bl2_secure_setting(); 250 251 reg = mmio_read_32(RCAR_PRR); 252 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 253 product = reg & PRR_PRODUCT_MASK; 254 cut = reg & PRR_CUT_MASK; 255 256 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 257 goto tlb; 258 259 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 260 goto tlb; 261 262 if (product == PRR_PRODUCT_D3) 263 goto tlb; 264 265 /* Disable MFIS write protection */ 266 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 267 268 tlb: 269 reg = mmio_read_32(RCAR_MODEMR); 270 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 271 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 272 boot_cpu != MODEMR_BOOT_CPU_CA53) 273 goto mmu; 274 275 if (product_cut == PRR_PRODUCT_H3_CUT20) { 276 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 277 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 278 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 280 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 281 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 282 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 283 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 284 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 285 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 286 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 287 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 288 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 289 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 290 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 291 } 292 293 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 294 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 295 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 296 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 297 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 298 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 299 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 300 301 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 302 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 303 } 304 305 mmu: 306 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 307 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 308 309 val = rcar_rom_get_lcs(&lcs); 310 if (val) { 311 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 312 panic(); 313 } 314 315 if (lcs == LCS_SE) 316 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 317 318 rcar_swdt_release(); 319 bl2_system_cpg_init(); 320 321 #if RCAR_BL2_DCACHE == 1 322 /* Disable data cache (clean and invalidate) */ 323 disable_mmu_el3(); 324 #endif 325 } 326 327 static uint32_t is_ddr_backup_mode(void) 328 { 329 #if RCAR_SYSTEM_SUSPEND 330 static uint32_t reason = RCAR_COLD_BOOT; 331 static uint32_t once; 332 333 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 334 uint8_t data; 335 #endif 336 if (once) 337 return reason; 338 339 once = 1; 340 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 341 return reason; 342 343 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 344 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 345 ERROR("BL2: REG Keep10 READ ERROR.\n"); 346 panic(); 347 } 348 349 if (KEEP10_MAGIC != data) 350 reason = RCAR_WARM_BOOT; 351 #else 352 reason = RCAR_WARM_BOOT; 353 #endif 354 return reason; 355 #else 356 return RCAR_COLD_BOOT; 357 #endif 358 } 359 360 int bl2_plat_handle_pre_image_load(unsigned int image_id) 361 { 362 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 363 bl_mem_params_node_t *bl_mem_params; 364 365 if (image_id != BL31_IMAGE_ID) 366 return 0; 367 368 bl_mem_params = get_bl_mem_params_node(image_id); 369 370 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 371 goto cold_boot; 372 373 *boot_kind = RCAR_WARM_BOOT; 374 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 375 376 console_flush(); 377 bl2_plat_flush_bl31_params(); 378 379 /* will not return */ 380 bl2_enter_bl31(&bl_mem_params->ep_info); 381 382 cold_boot: 383 *boot_kind = RCAR_COLD_BOOT; 384 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 385 386 return 0; 387 } 388 389 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 390 { 391 uint32_t cert, len; 392 int ret; 393 394 ret = rcar_get_certificate(certid, &cert); 395 if (ret) { 396 ERROR("%s : cert file load error", __func__); 397 return 1; 398 } 399 400 rcar_read_certificate((uint64_t) cert, &len, dest); 401 402 return 0; 403 } 404 405 int bl2_plat_handle_post_image_load(unsigned int image_id) 406 { 407 static bl2_to_bl31_params_mem_t *params; 408 bl_mem_params_node_t *bl_mem_params; 409 uintptr_t dest; 410 int ret; 411 412 if (!params) { 413 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 414 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 415 } 416 417 bl_mem_params = get_bl_mem_params_node(image_id); 418 419 switch (image_id) { 420 case BL31_IMAGE_ID: 421 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 422 &dest); 423 if (!ret) 424 bl_mem_params->image_info.image_base = dest; 425 break; 426 case BL32_IMAGE_ID: 427 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 428 &dest); 429 if (!ret) 430 bl_mem_params->image_info.image_base = dest; 431 432 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 433 sizeof(entry_point_info_t)); 434 break; 435 case BL33_IMAGE_ID: 436 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 437 sizeof(entry_point_info_t)); 438 break; 439 } 440 441 return 0; 442 } 443 444 struct meminfo *bl2_plat_sec_mem_layout(void) 445 { 446 return &bl2_tzram_layout; 447 } 448 449 static void bl2_populate_compatible_string(void *dt) 450 { 451 uint32_t board_type; 452 uint32_t board_rev; 453 uint32_t reg; 454 int ret; 455 456 fdt_setprop_u32(dt, 0, "#address-cells", 2); 457 fdt_setprop_u32(dt, 0, "#size-cells", 2); 458 459 /* Populate compatible string */ 460 rcar_get_board_type(&board_type, &board_rev); 461 switch (board_type) { 462 case BOARD_SALVATOR_X: 463 ret = fdt_setprop_string(dt, 0, "compatible", 464 "renesas,salvator-x"); 465 break; 466 case BOARD_SALVATOR_XS: 467 ret = fdt_setprop_string(dt, 0, "compatible", 468 "renesas,salvator-xs"); 469 break; 470 case BOARD_STARTER_KIT: 471 ret = fdt_setprop_string(dt, 0, "compatible", 472 "renesas,m3ulcb"); 473 break; 474 case BOARD_STARTER_KIT_PRE: 475 ret = fdt_setprop_string(dt, 0, "compatible", 476 "renesas,h3ulcb"); 477 break; 478 case BOARD_EAGLE: 479 ret = fdt_setprop_string(dt, 0, "compatible", 480 "renesas,eagle"); 481 break; 482 case BOARD_EBISU: 483 case BOARD_EBISU_4D: 484 ret = fdt_setprop_string(dt, 0, "compatible", 485 "renesas,ebisu"); 486 break; 487 case BOARD_DRAAK: 488 ret = fdt_setprop_string(dt, 0, "compatible", 489 "renesas,draak"); 490 break; 491 default: 492 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 493 panic(); 494 } 495 496 if (ret < 0) { 497 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 498 panic(); 499 } 500 501 reg = mmio_read_32(RCAR_PRR); 502 switch (reg & PRR_PRODUCT_MASK) { 503 case PRR_PRODUCT_H3: 504 ret = fdt_appendprop_string(dt, 0, "compatible", 505 "renesas,r8a7795"); 506 break; 507 case PRR_PRODUCT_M3: 508 ret = fdt_appendprop_string(dt, 0, "compatible", 509 "renesas,r8a7796"); 510 break; 511 case PRR_PRODUCT_M3N: 512 ret = fdt_appendprop_string(dt, 0, "compatible", 513 "renesas,r8a77965"); 514 break; 515 case PRR_PRODUCT_V3M: 516 ret = fdt_appendprop_string(dt, 0, "compatible", 517 "renesas,r8a77970"); 518 break; 519 case PRR_PRODUCT_E3: 520 ret = fdt_appendprop_string(dt, 0, "compatible", 521 "renesas,r8a77990"); 522 break; 523 case PRR_PRODUCT_D3: 524 ret = fdt_appendprop_string(dt, 0, "compatible", 525 "renesas,r8a77995"); 526 break; 527 default: 528 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 529 panic(); 530 } 531 532 if (ret < 0) { 533 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 534 panic(); 535 } 536 } 537 538 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 539 { 540 char nodename[32] = { 0 }; 541 uint64_t start, size; 542 uint64_t fdtsize; 543 int ret, node, chan; 544 545 for (chan = 0; chan < 4; chan++) { 546 start = dram_config[2 * chan]; 547 size = dram_config[2 * chan + 1]; 548 if (!size) 549 continue; 550 551 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 552 chan, start, start + size - 1, 553 (size >> 30) ? : size >> 20, 554 (size >> 30) ? "G" : "M"); 555 } 556 557 /* 558 * We add the DT nodes in reverse order here. The fdt_add_subnode() 559 * adds the DT node before the first existing DT node, so we have 560 * to add them in reverse order to get nodes sorted by address in 561 * the resulting DT. 562 */ 563 for (chan = 3; chan >= 0; chan--) { 564 start = dram_config[2 * chan]; 565 size = dram_config[2 * chan + 1]; 566 if (!size) 567 continue; 568 569 /* 570 * Channel 0 is mapped in 32bit space and the first 571 * 128 MiB are reserved 572 */ 573 if (chan == 0) { 574 start = 0x48000000; 575 size -= 0x8000000; 576 } 577 578 fdtsize = cpu_to_fdt64(size); 579 580 snprintf(nodename, sizeof(nodename), "memory@"); 581 unsigned_num_print(start, 16, nodename + strlen(nodename)); 582 node = ret = fdt_add_subnode(fdt, 0, nodename); 583 if (ret < 0) 584 goto err; 585 586 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 587 if (ret < 0) 588 goto err; 589 590 ret = fdt_setprop_u64(fdt, node, "reg", start); 591 if (ret < 0) 592 goto err; 593 594 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 595 sizeof(fdtsize)); 596 if (ret < 0) 597 goto err; 598 } 599 600 return; 601 err: 602 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 603 panic(); 604 } 605 606 static void bl2_advertise_dram_size(uint32_t product) 607 { 608 uint64_t dram_config[8] = { 609 [0] = 0x400000000ULL, 610 [2] = 0x500000000ULL, 611 [4] = 0x600000000ULL, 612 [6] = 0x700000000ULL, 613 }; 614 615 switch (product) { 616 case PRR_PRODUCT_H3: 617 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 618 /* 4GB(1GBx4) */ 619 dram_config[1] = 0x40000000ULL; 620 dram_config[3] = 0x40000000ULL; 621 dram_config[5] = 0x40000000ULL; 622 dram_config[7] = 0x40000000ULL; 623 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 624 (RCAR_DRAM_CHANNEL == 5) && \ 625 (RCAR_DRAM_SPLIT == 2) 626 /* 4GB(2GBx2 2ch split) */ 627 dram_config[1] = 0x80000000ULL; 628 dram_config[3] = 0x80000000ULL; 629 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 630 /* 8GB(2GBx4: default) */ 631 dram_config[1] = 0x80000000ULL; 632 dram_config[3] = 0x80000000ULL; 633 dram_config[5] = 0x80000000ULL; 634 dram_config[7] = 0x80000000ULL; 635 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 636 break; 637 638 case PRR_PRODUCT_M3: 639 #if (RCAR_GEN3_ULCB == 1) 640 /* 2GB(1GBx2 2ch split) */ 641 dram_config[1] = 0x40000000ULL; 642 dram_config[5] = 0x40000000ULL; 643 #else 644 /* 4GB(2GBx2 2ch split) */ 645 dram_config[1] = 0x80000000ULL; 646 dram_config[5] = 0x80000000ULL; 647 #endif 648 break; 649 650 case PRR_PRODUCT_M3N: 651 /* 2GB(1GBx2) */ 652 dram_config[1] = 0x80000000ULL; 653 break; 654 655 case PRR_PRODUCT_V3M: 656 /* 1GB(512MBx2) */ 657 dram_config[1] = 0x40000000ULL; 658 break; 659 660 case PRR_PRODUCT_E3: 661 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 662 /* 1GB(512MBx2) */ 663 dram_config[1] = 0x40000000ULL; 664 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 665 /* 2GB(512MBx4) */ 666 dram_config[1] = 0x80000000ULL; 667 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 668 /* 4GB(1GBx4) */ 669 dram_config[1] = 0x100000000ULL; 670 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 671 break; 672 673 case PRR_PRODUCT_D3: 674 /* 512MB */ 675 dram_config[1] = 0x20000000ULL; 676 break; 677 } 678 679 bl2_advertise_dram_entries(dram_config); 680 } 681 682 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 683 u_register_t arg3, u_register_t arg4) 684 { 685 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 686 uint32_t product, product_cut, major, minor; 687 int32_t ret; 688 const char *str; 689 const char *unknown = "unknown"; 690 const char *cpu_ca57 = "CA57"; 691 const char *cpu_ca53 = "CA53"; 692 const char *product_m3n = "M3N"; 693 const char *product_h3 = "H3"; 694 const char *product_m3 = "M3"; 695 const char *product_e3 = "E3"; 696 const char *product_d3 = "D3"; 697 const char *product_v3m = "V3M"; 698 const char *lcs_secure = "SE"; 699 const char *lcs_cm = "CM"; 700 const char *lcs_dm = "DM"; 701 const char *lcs_sd = "SD"; 702 const char *lcs_fa = "FA"; 703 const char *sscg_off = "PLL1 nonSSCG Clock select"; 704 const char *sscg_on = "PLL1 SSCG Clock select"; 705 const char *boot_hyper80 = "HyperFlash(80MHz)"; 706 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 707 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 708 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 709 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 710 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 711 const char *boot_hyper160 = "HyperFlash(150MHz)"; 712 #else 713 const char *boot_hyper160 = "HyperFlash(160MHz)"; 714 #endif 715 #if (RCAR_LOSSY_ENABLE == 1) 716 int fcnlnode; 717 #endif 718 719 bl2_init_generic_timer(); 720 721 reg = mmio_read_32(RCAR_MODEMR); 722 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 723 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 724 725 bl2_cpg_init(); 726 727 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 728 boot_cpu == MODEMR_BOOT_CPU_CA53) { 729 rcar_pfc_init(); 730 rcar_console_boot_init(); 731 } 732 733 plat_rcar_gic_driver_init(); 734 plat_rcar_gic_init(); 735 rcar_swdt_init(); 736 737 /* FIQ interrupts are taken to EL3 */ 738 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 739 740 write_daifclr(DAIF_FIQ_BIT); 741 742 reg = read_midr(); 743 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 744 switch (midr) { 745 case MIDR_CA57: 746 str = cpu_ca57; 747 break; 748 case MIDR_CA53: 749 str = cpu_ca53; 750 break; 751 default: 752 str = unknown; 753 break; 754 } 755 756 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 757 version_of_renesas); 758 759 reg = mmio_read_32(RCAR_PRR); 760 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 761 product = reg & PRR_PRODUCT_MASK; 762 763 switch (product) { 764 case PRR_PRODUCT_H3: 765 str = product_h3; 766 break; 767 case PRR_PRODUCT_M3: 768 str = product_m3; 769 break; 770 case PRR_PRODUCT_M3N: 771 str = product_m3n; 772 break; 773 case PRR_PRODUCT_V3M: 774 str = product_v3m; 775 break; 776 case PRR_PRODUCT_E3: 777 str = product_e3; 778 break; 779 case PRR_PRODUCT_D3: 780 str = product_d3; 781 break; 782 default: 783 str = unknown; 784 break; 785 } 786 787 if ((PRR_PRODUCT_M3 == product) && 788 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 789 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 790 /* M3 Ver.1.1 or Ver.1.2 */ 791 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 792 str); 793 } else { 794 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 795 str, 796 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 797 } 798 } else { 799 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 800 major = major + RCAR_MAJOR_OFFSET; 801 minor = reg & RCAR_MINOR_MASK; 802 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 803 } 804 805 if (product == PRR_PRODUCT_E3) { 806 reg = mmio_read_32(RCAR_MODEMR); 807 sscg = reg & RCAR_SSCG_MASK; 808 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 809 NOTICE("BL2: %s\n", str); 810 } 811 812 rcar_get_board_type(&type, &rev); 813 814 switch (type) { 815 case BOARD_SALVATOR_X: 816 case BOARD_KRIEK: 817 case BOARD_STARTER_KIT: 818 case BOARD_SALVATOR_XS: 819 case BOARD_EBISU: 820 case BOARD_STARTER_KIT_PRE: 821 case BOARD_EBISU_4D: 822 case BOARD_DRAAK: 823 case BOARD_EAGLE: 824 break; 825 default: 826 type = BOARD_UNKNOWN; 827 break; 828 } 829 830 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 831 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 832 else { 833 NOTICE("BL2: Board is %s Rev.%d.%d\n", 834 GET_BOARD_NAME(type), 835 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 836 } 837 838 #if RCAR_LSI != RCAR_AUTO 839 if (product != TARGET_PRODUCT) { 840 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 841 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 842 panic(); 843 } 844 #endif 845 rcar_avs_init(); 846 rcar_avs_setting(); 847 848 switch (boot_dev) { 849 case MODEMR_BOOT_DEV_HYPERFLASH160: 850 str = boot_hyper160; 851 break; 852 case MODEMR_BOOT_DEV_HYPERFLASH80: 853 str = boot_hyper80; 854 break; 855 case MODEMR_BOOT_DEV_QSPI_FLASH40: 856 str = boot_qspi40; 857 break; 858 case MODEMR_BOOT_DEV_QSPI_FLASH80: 859 str = boot_qspi80; 860 break; 861 case MODEMR_BOOT_DEV_EMMC_25X1: 862 #if RCAR_LSI == RCAR_D3 863 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 864 panic(); 865 #endif 866 str = boot_emmc25x1; 867 break; 868 case MODEMR_BOOT_DEV_EMMC_50X8: 869 #if RCAR_LSI == RCAR_D3 870 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 871 panic(); 872 #endif 873 str = boot_emmc50x8; 874 break; 875 default: 876 str = unknown; 877 break; 878 } 879 NOTICE("BL2: Boot device is %s\n", str); 880 881 rcar_avs_setting(); 882 reg = rcar_rom_get_lcs(&lcs); 883 if (reg) { 884 str = unknown; 885 goto lcm_state; 886 } 887 888 switch (lcs) { 889 case LCS_CM: 890 str = lcs_cm; 891 break; 892 case LCS_DM: 893 str = lcs_dm; 894 break; 895 case LCS_SD: 896 str = lcs_sd; 897 break; 898 case LCS_SE: 899 str = lcs_secure; 900 break; 901 case LCS_FA: 902 str = lcs_fa; 903 break; 904 default: 905 str = unknown; 906 break; 907 } 908 909 lcm_state: 910 NOTICE("BL2: LCM state is %s\n", str); 911 912 rcar_avs_end(); 913 is_ddr_backup_mode(); 914 915 bl2_tzram_layout.total_base = BL31_BASE; 916 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 917 918 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 919 boot_cpu == MODEMR_BOOT_CPU_CA53) { 920 ret = rcar_dram_init(); 921 if (ret) { 922 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 923 panic(); 924 } 925 rcar_qos_init(); 926 } 927 928 /* Set up FDT */ 929 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 930 if (ret) { 931 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 932 panic(); 933 } 934 935 /* Add platform compatible string */ 936 bl2_populate_compatible_string(fdt); 937 938 /* Print DRAM layout */ 939 bl2_advertise_dram_size(product); 940 941 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 942 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 943 if (rcar_emmc_init() != EMMC_SUCCESS) { 944 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 945 panic(); 946 } 947 rcar_emmc_memcard_power(EMMC_POWER_ON); 948 if (rcar_emmc_mount() != EMMC_SUCCESS) { 949 NOTICE("BL2: Failed to eMMC mount operation.\n"); 950 panic(); 951 } 952 } else { 953 rcar_rpc_init(); 954 rcar_dma_init(); 955 } 956 957 reg = mmio_read_32(RST_WDTRSTCR); 958 reg &= ~WDTRSTCR_RWDT_RSTMSK; 959 reg |= WDTRSTCR_PASSWORD; 960 mmio_write_32(RST_WDTRSTCR, reg); 961 962 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 963 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 964 965 reg = mmio_read_32(RCAR_PRR); 966 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 967 mmio_write_32(CPG_CA57DBGRCR, 968 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 969 970 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 971 mmio_write_32(CPG_CA53DBGRCR, 972 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 973 974 if (product_cut == PRR_PRODUCT_H3_CUT10) { 975 reg = mmio_read_32(CPG_PLL2CR); 976 reg &= ~((uint32_t) 1 << 5); 977 mmio_write_32(CPG_PLL2CR, reg); 978 979 reg = mmio_read_32(CPG_PLL4CR); 980 reg &= ~((uint32_t) 1 << 5); 981 mmio_write_32(CPG_PLL4CR, reg); 982 983 reg = mmio_read_32(CPG_PLL0CR); 984 reg &= ~((uint32_t) 1 << 12); 985 mmio_write_32(CPG_PLL0CR, reg); 986 } 987 #if (RCAR_LOSSY_ENABLE == 1) 988 NOTICE("BL2: Lossy Decomp areas\n"); 989 990 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 991 if (fcnlnode < 0) { 992 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 993 fcnlnode); 994 panic(); 995 } 996 997 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 998 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 999 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 1000 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 1001 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 1002 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 1003 #endif 1004 1005 fdt_pack(fdt); 1006 NOTICE("BL2: FDT at %p\n", fdt); 1007 1008 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1009 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1010 rcar_io_emmc_setup(); 1011 else 1012 rcar_io_setup(); 1013 } 1014 1015 void bl2_el3_plat_arch_setup(void) 1016 { 1017 #if RCAR_BL2_DCACHE == 1 1018 NOTICE("BL2: D-Cache enable\n"); 1019 rcar_configure_mmu_el3(BL2_BASE, 1020 BL2_END - BL2_BASE, 1021 BL2_RO_BASE, BL2_RO_LIMIT 1022 #if USE_COHERENT_MEM 1023 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1024 #endif 1025 ); 1026 #endif 1027 } 1028 1029 void bl2_platform_setup(void) 1030 { 1031 1032 } 1033 1034 static void bl2_init_generic_timer(void) 1035 { 1036 /* FIXME: V3M 16.666 MHz ? */ 1037 #if RCAR_LSI == RCAR_D3 1038 uint32_t reg_cntfid = EXTAL_DRAAK; 1039 #elif RCAR_LSI == RCAR_E3 1040 uint32_t reg_cntfid = EXTAL_EBISU; 1041 #else /* RCAR_LSI == RCAR_E3 */ 1042 uint32_t reg; 1043 uint32_t reg_cntfid; 1044 uint32_t modemr; 1045 uint32_t modemr_pll; 1046 uint32_t board_type; 1047 uint32_t board_rev; 1048 uint32_t pll_table[] = { 1049 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1050 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1051 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1052 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1053 }; 1054 1055 modemr = mmio_read_32(RCAR_MODEMR); 1056 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1057 1058 /* Set frequency data in CNTFID0 */ 1059 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1060 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1061 switch (modemr_pll) { 1062 case MD14_MD13_TYPE_0: 1063 rcar_get_board_type(&board_type, &board_rev); 1064 if (BOARD_SALVATOR_XS == board_type) { 1065 reg_cntfid = EXTAL_SALVATOR_XS; 1066 } 1067 break; 1068 case MD14_MD13_TYPE_3: 1069 if (PRR_PRODUCT_H3_CUT10 == reg) { 1070 reg_cntfid = reg_cntfid >> 1U; 1071 } 1072 break; 1073 default: 1074 /* none */ 1075 break; 1076 } 1077 #endif /* RCAR_LSI == RCAR_E3 */ 1078 /* Update memory mapped and register based freqency */ 1079 write_cntfrq_el0((u_register_t )reg_cntfid); 1080 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1081 /* Enable counter */ 1082 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1083 (uint32_t)CNTCR_EN); 1084 } 1085