1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <desc_image_load.h> 8 #include <arch_helpers.h> 9 #include <bl_common.h> 10 #include <bl1.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <libfdt.h> 14 #include <mmio.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <string.h> 18 #include <xlat_tables_defs.h> 19 20 #include "avs_driver.h" 21 #include "boot_init_dram.h" 22 #include "cpg_registers.h" 23 #include "board.h" 24 #include "emmc_def.h" 25 #include "emmc_hal.h" 26 #include "emmc_std.h" 27 28 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 29 #include "iic_dvfs.h" 30 #endif 31 32 #include "io_common.h" 33 #include "qos_init.h" 34 #include "rcar_def.h" 35 #include "rcar_private.h" 36 #include "rcar_version.h" 37 #include "rom_api.h" 38 39 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 40 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 41 42 #if USE_COHERENT_MEM 43 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 44 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 45 #endif 46 47 extern void plat_rcar_gic_driver_init(void); 48 extern void plat_rcar_gic_init(void); 49 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 50 extern void bl2_system_cpg_init(void); 51 extern void bl2_secure_setting(void); 52 extern void bl2_cpg_init(void); 53 extern void rcar_io_emmc_setup(void); 54 extern void rcar_io_setup(void); 55 extern void rcar_swdt_release(void); 56 extern void rcar_swdt_init(void); 57 extern void rcar_rpc_init(void); 58 extern void rcar_pfc_init(void); 59 extern void rcar_dma_init(void); 60 61 /* R-Car Gen3 product check */ 62 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 63 #define TARGET_PRODUCT RCAR_PRODUCT_H3 64 #define TARGET_NAME "R-Car H3" 65 #elif RCAR_LSI == RCAR_M3 66 #define TARGET_PRODUCT RCAR_PRODUCT_M3 67 #define TARGET_NAME "R-Car M3" 68 #elif RCAR_LSI == RCAR_M3N 69 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 70 #define TARGET_NAME "R-Car M3N" 71 #elif RCAR_LSI == RCAR_E3 72 #define TARGET_PRODUCT RCAR_PRODUCT_E3 73 #define TARGET_NAME "R-Car E3" 74 #endif 75 76 #if (RCAR_LSI == RCAR_E3) 77 #define GPIO_INDT (GPIO_INDT6) 78 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 79 #else 80 #define GPIO_INDT (GPIO_INDT1) 81 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 82 #endif 83 84 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 85 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 86 assert_bl31_params_do_not_fit_in_shared_memory); 87 88 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 89 90 /* FDT with DRAM configuration */ 91 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 92 static void *fdt = (void *)fdt_blob; 93 94 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 95 char *string) 96 { 97 /* Just need enough space to store 64 bit decimal integer */ 98 char num_buf[20]; 99 int i = 0; 100 unsigned int rem; 101 102 do { 103 rem = unum % radix; 104 if (rem < 0xa) 105 num_buf[i] = '0' + rem; 106 else 107 num_buf[i] = 'a' + (rem - 0xa); 108 i++; 109 unum /= radix; 110 } while (unum > 0U); 111 112 while (--i >= 0) 113 *string++ = num_buf[i]; 114 } 115 116 #if (RCAR_LOSSY_ENABLE == 1) 117 typedef struct bl2_lossy_info { 118 uint32_t magic; 119 uint32_t a0; 120 uint32_t b0; 121 } bl2_lossy_info_t; 122 123 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 124 uint64_t end_addr, uint32_t format, 125 uint32_t enable) 126 { 127 bl2_lossy_info_t info; 128 uint32_t reg; 129 130 reg = format | (start_addr >> 20); 131 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 132 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 133 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 134 135 info.magic = 0x12345678U; 136 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 137 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 138 139 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 140 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 141 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 142 143 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 144 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 145 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 146 } 147 #endif 148 149 void bl2_plat_flush_bl31_params(void) 150 { 151 uint32_t product_cut, product, cut; 152 uint32_t boot_dev, boot_cpu; 153 uint32_t lcs, reg, val; 154 155 reg = mmio_read_32(RCAR_MODEMR); 156 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 157 158 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 159 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 160 emmc_terminate(); 161 162 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 163 bl2_secure_setting(); 164 165 reg = mmio_read_32(RCAR_PRR); 166 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 167 product = reg & RCAR_PRODUCT_MASK; 168 cut = reg & RCAR_CUT_MASK; 169 170 if (product == RCAR_PRODUCT_M3) 171 goto tlb; 172 173 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 174 goto tlb; 175 176 /* Disable MFIS write protection */ 177 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 178 179 tlb: 180 reg = mmio_read_32(RCAR_MODEMR); 181 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 182 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 183 boot_cpu != MODEMR_BOOT_CPU_CA53) 184 goto mmu; 185 186 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 187 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 188 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 189 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 190 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 191 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 192 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 193 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 194 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 195 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 196 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 197 } else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 198 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 199 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 200 } 201 202 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 203 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 204 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 205 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 206 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 207 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 208 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 209 210 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 211 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 212 } 213 214 mmu: 215 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 216 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 217 218 val = rcar_rom_get_lcs(&lcs); 219 if (val) { 220 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 221 panic(); 222 } 223 224 if (lcs == LCS_SE) 225 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 226 227 rcar_swdt_release(); 228 bl2_system_cpg_init(); 229 230 #if RCAR_BL2_DCACHE == 1 231 /* Disable data cache (clean and invalidate) */ 232 disable_mmu_el3(); 233 #endif 234 } 235 236 static uint32_t is_ddr_backup_mode(void) 237 { 238 #if RCAR_SYSTEM_SUSPEND 239 static uint32_t reason = RCAR_COLD_BOOT; 240 static uint32_t once; 241 242 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 243 uint8_t data; 244 #endif 245 if (once) 246 return reason; 247 248 once = 1; 249 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 250 return reason; 251 252 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 253 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 254 ERROR("BL2: REG Keep10 READ ERROR.\n"); 255 panic(); 256 } 257 258 if (KEEP10_MAGIC != data) 259 reason = RCAR_WARM_BOOT; 260 #else 261 reason = RCAR_WARM_BOOT; 262 #endif 263 return reason; 264 #else 265 return RCAR_COLD_BOOT; 266 #endif 267 } 268 269 int bl2_plat_handle_pre_image_load(unsigned int image_id) 270 { 271 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 272 bl_mem_params_node_t *bl_mem_params; 273 274 if (image_id != BL31_IMAGE_ID) 275 return 0; 276 277 bl_mem_params = get_bl_mem_params_node(image_id); 278 279 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 280 goto cold_boot; 281 282 *boot_kind = RCAR_WARM_BOOT; 283 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 284 285 console_flush(); 286 bl2_plat_flush_bl31_params(); 287 288 /* will not return */ 289 bl2_enter_bl31(&bl_mem_params->ep_info); 290 291 cold_boot: 292 *boot_kind = RCAR_COLD_BOOT; 293 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 294 295 return 0; 296 } 297 298 int bl2_plat_handle_post_image_load(unsigned int image_id) 299 { 300 static bl2_to_bl31_params_mem_t *params; 301 bl_mem_params_node_t *bl_mem_params; 302 303 if (!params) { 304 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 305 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 306 } 307 308 bl_mem_params = get_bl_mem_params_node(image_id); 309 310 switch (image_id) { 311 case BL31_IMAGE_ID: 312 break; 313 case BL32_IMAGE_ID: 314 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 315 sizeof(entry_point_info_t)); 316 break; 317 case BL33_IMAGE_ID: 318 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 319 sizeof(entry_point_info_t)); 320 break; 321 } 322 323 return 0; 324 } 325 326 meminfo_t *bl2_plat_sec_mem_layout(void) 327 { 328 return &bl2_tzram_layout; 329 } 330 331 static void bl2_populate_compatible_string(void *fdt) 332 { 333 uint32_t board_type; 334 uint32_t board_rev; 335 uint32_t reg; 336 int ret; 337 338 /* Populate compatible string */ 339 rcar_get_board_type(&board_type, &board_rev); 340 switch (board_type) { 341 case BOARD_SALVATOR_X: 342 ret = fdt_setprop_string(fdt, 0, "compatible", 343 "renesas,salvator-x"); 344 break; 345 case BOARD_SALVATOR_XS: 346 ret = fdt_setprop_string(fdt, 0, "compatible", 347 "renesas,salvator-xs"); 348 break; 349 case BOARD_STARTER_KIT: 350 ret = fdt_setprop_string(fdt, 0, "compatible", 351 "renesas,m3ulcb"); 352 break; 353 case BOARD_STARTER_KIT_PRE: 354 ret = fdt_setprop_string(fdt, 0, "compatible", 355 "renesas,h3ulcb"); 356 break; 357 case BOARD_EBISU: 358 case BOARD_EBISU_4D: 359 ret = fdt_setprop_string(fdt, 0, "compatible", 360 "renesas,ebisu"); 361 break; 362 default: 363 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 364 panic(); 365 } 366 367 if (ret < 0) { 368 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 369 panic(); 370 } 371 372 reg = mmio_read_32(RCAR_PRR); 373 switch (reg & RCAR_PRODUCT_MASK) { 374 case RCAR_PRODUCT_H3: 375 ret = fdt_appendprop_string(fdt, 0, "compatible", 376 "renesas,r8a7795"); 377 break; 378 case RCAR_PRODUCT_M3: 379 ret = fdt_appendprop_string(fdt, 0, "compatible", 380 "renesas,r8a7796"); 381 break; 382 case RCAR_PRODUCT_M3N: 383 ret = fdt_appendprop_string(fdt, 0, "compatible", 384 "renesas,r8a77965"); 385 break; 386 case RCAR_PRODUCT_E3: 387 ret = fdt_appendprop_string(fdt, 0, "compatible", 388 "renesas,r8a77990"); 389 break; 390 default: 391 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 392 panic(); 393 } 394 395 if (ret < 0) { 396 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 397 panic(); 398 } 399 } 400 401 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 402 { 403 char nodename[32] = { 0 }; 404 uint64_t start, size; 405 uint64_t fdtsize; 406 int ret, node, chan; 407 408 for (chan = 0; chan < 4; chan++) { 409 start = dram_config[2 * chan]; 410 size = dram_config[2 * chan + 1]; 411 if (!size) 412 continue; 413 414 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 415 chan, start, start + size - 1, size >> 30); 416 } 417 418 /* 419 * We add the DT nodes in reverse order here. The fdt_add_subnode() 420 * adds the DT node before the first existing DT node, so we have 421 * to add them in reverse order to get nodes sorted by address in 422 * the resulting DT. 423 */ 424 for (chan = 3; chan >= 0; chan--) { 425 start = dram_config[2 * chan]; 426 size = dram_config[2 * chan + 1]; 427 if (!size) 428 continue; 429 430 /* 431 * Channel 0 is mapped in 32bit space and the first 432 * 128 MiB are reserved 433 */ 434 if (chan == 0) { 435 start = 0x48000000; 436 size -= 0x8000000; 437 } 438 439 fdtsize = cpu_to_fdt64(size); 440 441 snprintf(nodename, sizeof(nodename), "memory@"); 442 unsigned_num_print(start, 16, nodename + strlen(nodename)); 443 node = ret = fdt_add_subnode(fdt, 0, nodename); 444 if (ret < 0) 445 goto err; 446 447 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 448 if (ret < 0) 449 goto err; 450 451 ret = fdt_setprop_u64(fdt, node, "reg", start); 452 if (ret < 0) 453 goto err; 454 455 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 456 sizeof(fdtsize)); 457 if (ret < 0) 458 goto err; 459 } 460 461 return; 462 err: 463 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 464 panic(); 465 } 466 467 static void bl2_advertise_dram_size(uint32_t product) 468 { 469 uint64_t dram_config[8] = { 470 [0] = 0x400000000ULL, 471 [2] = 0x500000000ULL, 472 [4] = 0x600000000ULL, 473 [6] = 0x700000000ULL, 474 }; 475 476 switch (product) { 477 case RCAR_PRODUCT_H3: 478 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 479 /* 4GB(1GBx4) */ 480 dram_config[1] = 0x40000000ULL; 481 dram_config[3] = 0x40000000ULL; 482 dram_config[5] = 0x40000000ULL; 483 dram_config[7] = 0x40000000ULL; 484 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 485 (RCAR_DRAM_CHANNEL == 5) && \ 486 (RCAR_DRAM_SPLIT == 2) 487 /* 4GB(2GBx2 2ch split) */ 488 dram_config[1] = 0x80000000ULL; 489 dram_config[3] = 0x80000000ULL; 490 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 491 /* 8GB(2GBx4: default) */ 492 dram_config[1] = 0x80000000ULL; 493 dram_config[3] = 0x80000000ULL; 494 dram_config[5] = 0x80000000ULL; 495 dram_config[7] = 0x80000000ULL; 496 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 497 break; 498 499 case RCAR_PRODUCT_M3: 500 /* 4GB(2GBx2 2ch split) */ 501 dram_config[1] = 0x80000000ULL; 502 dram_config[5] = 0x80000000ULL; 503 break; 504 505 case RCAR_PRODUCT_M3N: 506 /* 2GB(1GBx2) */ 507 dram_config[1] = 0x80000000ULL; 508 break; 509 510 case RCAR_PRODUCT_E3: 511 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 512 /* 1GB(512MBx2) */ 513 dram_config[1] = 0x40000000ULL; 514 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 515 /* 2GB(512MBx4) */ 516 dram_config[1] = 0x80000000ULL; 517 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 518 /* 4GB(1GBx4) */ 519 dram_config[1] = 0x100000000ULL; 520 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 521 break; 522 } 523 524 bl2_advertise_dram_entries(dram_config); 525 } 526 527 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 528 u_register_t arg3, u_register_t arg4) 529 { 530 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 531 uint32_t product, product_cut, major, minor; 532 int32_t ret; 533 const char *str; 534 const char *unknown = "unknown"; 535 const char *cpu_ca57 = "CA57"; 536 const char *cpu_ca53 = "CA53"; 537 const char *product_m3n = "M3N"; 538 const char *product_h3 = "H3"; 539 const char *product_m3 = "M3"; 540 const char *product_e3 = "E3"; 541 const char *lcs_secure = "SE"; 542 const char *lcs_cm = "CM"; 543 const char *lcs_dm = "DM"; 544 const char *lcs_sd = "SD"; 545 const char *lcs_fa = "FA"; 546 const char *sscg_off = "PLL1 nonSSCG Clock select"; 547 const char *sscg_on = "PLL1 SSCG Clock select"; 548 const char *boot_hyper80 = "HyperFlash(80MHz)"; 549 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 550 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 551 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 552 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 553 #if RCAR_LSI == RCAR_E3 554 const char *boot_hyper160 = "HyperFlash(150MHz)"; 555 #else 556 const char *boot_hyper160 = "HyperFlash(160MHz)"; 557 #endif 558 559 reg = mmio_read_32(RCAR_MODEMR); 560 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 561 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 562 563 bl2_cpg_init(); 564 565 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 566 boot_cpu == MODEMR_BOOT_CPU_CA53) { 567 rcar_pfc_init(); 568 /* console configuration (platform specific) done in driver */ 569 console_init(0, 0, 0); 570 } 571 572 plat_rcar_gic_driver_init(); 573 plat_rcar_gic_init(); 574 rcar_swdt_init(); 575 576 /* FIQ interrupts are taken to EL3 */ 577 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 578 579 write_daifclr(DAIF_FIQ_BIT); 580 581 reg = read_midr(); 582 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 583 switch (midr) { 584 case MIDR_CA57: 585 str = cpu_ca57; 586 break; 587 case MIDR_CA53: 588 str = cpu_ca53; 589 break; 590 default: 591 str = unknown; 592 break; 593 } 594 595 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 596 version_of_renesas); 597 598 reg = mmio_read_32(RCAR_PRR); 599 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 600 product = reg & RCAR_PRODUCT_MASK; 601 602 switch (product) { 603 case RCAR_PRODUCT_H3: 604 str = product_h3; 605 break; 606 case RCAR_PRODUCT_M3: 607 str = product_m3; 608 break; 609 case RCAR_PRODUCT_M3N: 610 str = product_m3n; 611 break; 612 case RCAR_PRODUCT_E3: 613 str = product_e3; 614 break; 615 default: 616 str = unknown; 617 break; 618 } 619 620 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 621 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 622 } else { 623 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 624 major = major + RCAR_MAJOR_OFFSET; 625 minor = reg & RCAR_MINOR_MASK; 626 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 627 } 628 629 if (product == RCAR_PRODUCT_E3) { 630 reg = mmio_read_32(RCAR_MODEMR); 631 sscg = reg & RCAR_SSCG_MASK; 632 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 633 NOTICE("BL2: %s\n", str); 634 } 635 636 rcar_get_board_type(&type, &rev); 637 638 switch (type) { 639 case BOARD_SALVATOR_X: 640 case BOARD_KRIEK: 641 case BOARD_STARTER_KIT: 642 case BOARD_SALVATOR_XS: 643 case BOARD_EBISU: 644 case BOARD_STARTER_KIT_PRE: 645 case BOARD_EBISU_4D: 646 break; 647 default: 648 type = BOARD_UNKNOWN; 649 break; 650 } 651 652 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 653 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 654 else { 655 NOTICE("BL2: Board is %s Rev.%d.%d\n", 656 GET_BOARD_NAME(type), 657 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 658 } 659 660 #if RCAR_LSI != RCAR_AUTO 661 if (product != TARGET_PRODUCT) { 662 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 663 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 664 panic(); 665 } 666 #endif 667 rcar_avs_init(); 668 rcar_avs_setting(); 669 670 switch (boot_dev) { 671 case MODEMR_BOOT_DEV_HYPERFLASH160: 672 str = boot_hyper160; 673 break; 674 case MODEMR_BOOT_DEV_HYPERFLASH80: 675 str = boot_hyper80; 676 break; 677 case MODEMR_BOOT_DEV_QSPI_FLASH40: 678 str = boot_qspi40; 679 break; 680 case MODEMR_BOOT_DEV_QSPI_FLASH80: 681 str = boot_qspi80; 682 break; 683 case MODEMR_BOOT_DEV_EMMC_25X1: 684 str = boot_emmc25x1; 685 break; 686 case MODEMR_BOOT_DEV_EMMC_50X8: 687 str = boot_emmc50x8; 688 break; 689 default: 690 str = unknown; 691 break; 692 } 693 NOTICE("BL2: Boot device is %s\n", str); 694 695 rcar_avs_setting(); 696 reg = rcar_rom_get_lcs(&lcs); 697 if (reg) { 698 str = unknown; 699 goto lcm_state; 700 } 701 702 switch (lcs) { 703 case LCS_CM: 704 str = lcs_cm; 705 break; 706 case LCS_DM: 707 str = lcs_dm; 708 break; 709 case LCS_SD: 710 str = lcs_sd; 711 break; 712 case LCS_SE: 713 str = lcs_secure; 714 break; 715 case LCS_FA: 716 str = lcs_fa; 717 break; 718 default: 719 str = unknown; 720 break; 721 } 722 723 lcm_state: 724 NOTICE("BL2: LCM state is %s\n", str); 725 726 rcar_avs_end(); 727 is_ddr_backup_mode(); 728 729 bl2_tzram_layout.total_base = BL31_BASE; 730 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 731 732 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 733 boot_cpu == MODEMR_BOOT_CPU_CA53) { 734 ret = rcar_dram_init(); 735 if (ret) { 736 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 737 panic(); 738 } 739 rcar_qos_init(); 740 } 741 742 /* Set up FDT */ 743 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 744 if (ret) { 745 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 746 panic(); 747 } 748 749 /* Add platform compatible string */ 750 bl2_populate_compatible_string(fdt); 751 752 /* Print DRAM layout */ 753 bl2_advertise_dram_size(product); 754 755 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 756 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 757 if (rcar_emmc_init() != EMMC_SUCCESS) { 758 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 759 panic(); 760 } 761 rcar_emmc_memcard_power(EMMC_POWER_ON); 762 if (rcar_emmc_mount() != EMMC_SUCCESS) { 763 NOTICE("BL2: Failed to eMMC mount operation.\n"); 764 panic(); 765 } 766 } else { 767 rcar_rpc_init(); 768 rcar_dma_init(); 769 } 770 771 reg = mmio_read_32(RST_WDTRSTCR); 772 reg &= ~WDTRSTCR_RWDT_RSTMSK; 773 reg |= WDTRSTCR_PASSWORD; 774 mmio_write_32(RST_WDTRSTCR, reg); 775 776 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 777 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 778 779 reg = mmio_read_32(RCAR_PRR); 780 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 781 mmio_write_32(CPG_CA57DBGRCR, 782 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 783 784 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 785 mmio_write_32(CPG_CA53DBGRCR, 786 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 787 788 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 789 reg = mmio_read_32(CPG_PLL2CR); 790 reg &= ~((uint32_t) 1 << 5); 791 mmio_write_32(CPG_PLL2CR, reg); 792 793 reg = mmio_read_32(CPG_PLL4CR); 794 reg &= ~((uint32_t) 1 << 5); 795 mmio_write_32(CPG_PLL4CR, reg); 796 797 reg = mmio_read_32(CPG_PLL0CR); 798 reg &= ~((uint32_t) 1 << 12); 799 mmio_write_32(CPG_PLL0CR, reg); 800 } 801 #if (RCAR_LOSSY_ENABLE == 1) 802 NOTICE("BL2: Lossy Decomp areas\n"); 803 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 804 LOSSY_FMT0, LOSSY_ENA_DIS0); 805 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 806 LOSSY_FMT1, LOSSY_ENA_DIS1); 807 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 808 LOSSY_FMT2, LOSSY_ENA_DIS2); 809 #endif 810 811 fdt_pack(fdt); 812 NOTICE("BL2: FDT at %p\n", fdt); 813 814 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 815 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 816 rcar_io_emmc_setup(); 817 else 818 rcar_io_setup(); 819 } 820 821 void bl2_el3_plat_arch_setup(void) 822 { 823 #if RCAR_BL2_DCACHE == 1 824 NOTICE("BL2: D-Cache enable\n"); 825 rcar_configure_mmu_el3(BL2_BASE, 826 RCAR_SYSRAM_LIMIT - BL2_BASE, 827 BL2_RO_BASE, BL2_RO_LIMIT 828 #if USE_COHERENT_MEM 829 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 830 #endif 831 ); 832 #endif 833 } 834 835 void bl2_platform_setup(void) 836 { 837 838 } 839