1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 44 45 #if USE_COHERENT_MEM 46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 48 #endif 49 50 extern void plat_rcar_gic_driver_init(void); 51 extern void plat_rcar_gic_init(void); 52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 53 extern void bl2_system_cpg_init(void); 54 extern void bl2_secure_setting(void); 55 extern void bl2_cpg_init(void); 56 extern void rcar_io_emmc_setup(void); 57 extern void rcar_io_setup(void); 58 extern void rcar_swdt_release(void); 59 extern void rcar_swdt_init(void); 60 extern void rcar_rpc_init(void); 61 extern void rcar_pfc_init(void); 62 extern void rcar_dma_init(void); 63 64 static void bl2_init_generic_timer(void); 65 66 /* R-Car Gen3 product check */ 67 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 68 #define TARGET_PRODUCT RCAR_PRODUCT_H3 69 #define TARGET_NAME "R-Car H3" 70 #elif RCAR_LSI == RCAR_M3 71 #define TARGET_PRODUCT RCAR_PRODUCT_M3 72 #define TARGET_NAME "R-Car M3" 73 #elif RCAR_LSI == RCAR_M3N 74 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 75 #define TARGET_NAME "R-Car M3N" 76 #elif RCAR_LSI == RCAR_E3 77 #define TARGET_PRODUCT RCAR_PRODUCT_E3 78 #define TARGET_NAME "R-Car E3" 79 #elif RCAR_LSI == RCAR_AUTO 80 #define TARGET_NAME "R-Car H3/M3/M3N" 81 #endif 82 83 #if (RCAR_LSI == RCAR_E3) 84 #define GPIO_INDT (GPIO_INDT6) 85 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 86 #else 87 #define GPIO_INDT (GPIO_INDT1) 88 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 89 #endif 90 91 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 92 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 93 assert_bl31_params_do_not_fit_in_shared_memory); 94 95 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 96 97 /* FDT with DRAM configuration */ 98 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 99 static void *fdt = (void *)fdt_blob; 100 101 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 102 char *string) 103 { 104 /* Just need enough space to store 64 bit decimal integer */ 105 char num_buf[20]; 106 int i = 0; 107 unsigned int rem; 108 109 do { 110 rem = unum % radix; 111 if (rem < 0xa) 112 num_buf[i] = '0' + rem; 113 else 114 num_buf[i] = 'a' + (rem - 0xa); 115 i++; 116 unum /= radix; 117 } while (unum > 0U); 118 119 while (--i >= 0) 120 *string++ = num_buf[i]; 121 } 122 123 #if (RCAR_LOSSY_ENABLE == 1) 124 typedef struct bl2_lossy_info { 125 uint32_t magic; 126 uint32_t a0; 127 uint32_t b0; 128 } bl2_lossy_info_t; 129 130 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 131 uint64_t end_addr, uint32_t format, 132 uint32_t enable, int fcnlnode) 133 { 134 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 135 char nodename[40] = { 0 }; 136 int ret, node; 137 138 /* Ignore undefined addresses */ 139 if (start_addr == 0 && end_addr == 0) 140 return; 141 142 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 143 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 144 145 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 146 if (ret < 0) { 147 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 148 panic(); 149 } 150 151 ret = fdt_setprop_string(fdt, node, "compatible", 152 "renesas,lossy-decompression"); 153 if (ret < 0) { 154 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 155 panic(); 156 } 157 158 ret = fdt_appendprop_string(fdt, node, "compatible", 159 "shared-dma-pool"); 160 if (ret < 0) { 161 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 162 panic(); 163 } 164 165 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 166 if (ret < 0) { 167 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 168 panic(); 169 } 170 171 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 172 if (ret < 0) { 173 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 174 panic(); 175 } 176 177 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 178 if (ret < 0) { 179 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 180 panic(); 181 } 182 183 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 184 if (ret < 0) { 185 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 186 panic(); 187 } 188 } 189 190 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 191 uint64_t end_addr, uint32_t format, 192 uint32_t enable, int fcnlnode) 193 { 194 bl2_lossy_info_t info; 195 uint32_t reg; 196 197 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 198 199 reg = format | (start_addr >> 20); 200 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 201 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 202 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 203 204 info.magic = 0x12345678U; 205 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 206 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 207 208 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 209 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 210 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 211 212 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 213 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 214 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 215 } 216 #endif 217 218 void bl2_plat_flush_bl31_params(void) 219 { 220 uint32_t product_cut, product, cut; 221 uint32_t boot_dev, boot_cpu; 222 uint32_t lcs, reg, val; 223 224 reg = mmio_read_32(RCAR_MODEMR); 225 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 226 227 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 228 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 229 emmc_terminate(); 230 231 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 232 bl2_secure_setting(); 233 234 reg = mmio_read_32(RCAR_PRR); 235 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 236 product = reg & RCAR_PRODUCT_MASK; 237 cut = reg & RCAR_CUT_MASK; 238 239 if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut) 240 goto tlb; 241 242 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 243 goto tlb; 244 245 /* Disable MFIS write protection */ 246 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 247 248 tlb: 249 reg = mmio_read_32(RCAR_MODEMR); 250 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 251 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 252 boot_cpu != MODEMR_BOOT_CPU_CA53) 253 goto mmu; 254 255 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 256 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 257 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 258 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 259 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 260 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 261 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 262 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 263 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 264 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 265 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 266 } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || 267 (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { 268 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 269 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 270 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 271 } 272 273 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 274 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 275 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 276 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 277 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 278 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 280 281 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 282 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 283 } 284 285 mmu: 286 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 287 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 288 289 val = rcar_rom_get_lcs(&lcs); 290 if (val) { 291 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 292 panic(); 293 } 294 295 if (lcs == LCS_SE) 296 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 297 298 rcar_swdt_release(); 299 bl2_system_cpg_init(); 300 301 #if RCAR_BL2_DCACHE == 1 302 /* Disable data cache (clean and invalidate) */ 303 disable_mmu_el3(); 304 #endif 305 } 306 307 static uint32_t is_ddr_backup_mode(void) 308 { 309 #if RCAR_SYSTEM_SUSPEND 310 static uint32_t reason = RCAR_COLD_BOOT; 311 static uint32_t once; 312 313 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 314 uint8_t data; 315 #endif 316 if (once) 317 return reason; 318 319 once = 1; 320 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 321 return reason; 322 323 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 324 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 325 ERROR("BL2: REG Keep10 READ ERROR.\n"); 326 panic(); 327 } 328 329 if (KEEP10_MAGIC != data) 330 reason = RCAR_WARM_BOOT; 331 #else 332 reason = RCAR_WARM_BOOT; 333 #endif 334 return reason; 335 #else 336 return RCAR_COLD_BOOT; 337 #endif 338 } 339 340 int bl2_plat_handle_pre_image_load(unsigned int image_id) 341 { 342 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 343 bl_mem_params_node_t *bl_mem_params; 344 345 if (image_id != BL31_IMAGE_ID) 346 return 0; 347 348 bl_mem_params = get_bl_mem_params_node(image_id); 349 350 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 351 goto cold_boot; 352 353 *boot_kind = RCAR_WARM_BOOT; 354 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 355 356 console_flush(); 357 bl2_plat_flush_bl31_params(); 358 359 /* will not return */ 360 bl2_enter_bl31(&bl_mem_params->ep_info); 361 362 cold_boot: 363 *boot_kind = RCAR_COLD_BOOT; 364 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 365 366 return 0; 367 } 368 369 int bl2_plat_handle_post_image_load(unsigned int image_id) 370 { 371 static bl2_to_bl31_params_mem_t *params; 372 bl_mem_params_node_t *bl_mem_params; 373 374 if (!params) { 375 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 376 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 377 } 378 379 bl_mem_params = get_bl_mem_params_node(image_id); 380 381 switch (image_id) { 382 case BL31_IMAGE_ID: 383 break; 384 case BL32_IMAGE_ID: 385 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 386 sizeof(entry_point_info_t)); 387 break; 388 case BL33_IMAGE_ID: 389 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 390 sizeof(entry_point_info_t)); 391 break; 392 } 393 394 return 0; 395 } 396 397 struct meminfo *bl2_plat_sec_mem_layout(void) 398 { 399 return &bl2_tzram_layout; 400 } 401 402 static void bl2_populate_compatible_string(void *fdt) 403 { 404 uint32_t board_type; 405 uint32_t board_rev; 406 uint32_t reg; 407 int ret; 408 409 /* Populate compatible string */ 410 rcar_get_board_type(&board_type, &board_rev); 411 switch (board_type) { 412 case BOARD_SALVATOR_X: 413 ret = fdt_setprop_string(fdt, 0, "compatible", 414 "renesas,salvator-x"); 415 break; 416 case BOARD_SALVATOR_XS: 417 ret = fdt_setprop_string(fdt, 0, "compatible", 418 "renesas,salvator-xs"); 419 break; 420 case BOARD_STARTER_KIT: 421 ret = fdt_setprop_string(fdt, 0, "compatible", 422 "renesas,m3ulcb"); 423 break; 424 case BOARD_STARTER_KIT_PRE: 425 ret = fdt_setprop_string(fdt, 0, "compatible", 426 "renesas,h3ulcb"); 427 break; 428 case BOARD_EBISU: 429 case BOARD_EBISU_4D: 430 ret = fdt_setprop_string(fdt, 0, "compatible", 431 "renesas,ebisu"); 432 break; 433 default: 434 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 435 panic(); 436 } 437 438 if (ret < 0) { 439 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 440 panic(); 441 } 442 443 reg = mmio_read_32(RCAR_PRR); 444 switch (reg & RCAR_PRODUCT_MASK) { 445 case RCAR_PRODUCT_H3: 446 ret = fdt_appendprop_string(fdt, 0, "compatible", 447 "renesas,r8a7795"); 448 break; 449 case RCAR_PRODUCT_M3: 450 ret = fdt_appendprop_string(fdt, 0, "compatible", 451 "renesas,r8a7796"); 452 break; 453 case RCAR_PRODUCT_M3N: 454 ret = fdt_appendprop_string(fdt, 0, "compatible", 455 "renesas,r8a77965"); 456 break; 457 case RCAR_PRODUCT_E3: 458 ret = fdt_appendprop_string(fdt, 0, "compatible", 459 "renesas,r8a77990"); 460 break; 461 default: 462 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 463 panic(); 464 } 465 466 if (ret < 0) { 467 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 468 panic(); 469 } 470 } 471 472 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 473 { 474 char nodename[32] = { 0 }; 475 uint64_t start, size; 476 uint64_t fdtsize; 477 int ret, node, chan; 478 479 for (chan = 0; chan < 4; chan++) { 480 start = dram_config[2 * chan]; 481 size = dram_config[2 * chan + 1]; 482 if (!size) 483 continue; 484 485 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 486 chan, start, start + size - 1, size >> 30); 487 } 488 489 /* 490 * We add the DT nodes in reverse order here. The fdt_add_subnode() 491 * adds the DT node before the first existing DT node, so we have 492 * to add them in reverse order to get nodes sorted by address in 493 * the resulting DT. 494 */ 495 for (chan = 3; chan >= 0; chan--) { 496 start = dram_config[2 * chan]; 497 size = dram_config[2 * chan + 1]; 498 if (!size) 499 continue; 500 501 /* 502 * Channel 0 is mapped in 32bit space and the first 503 * 128 MiB are reserved 504 */ 505 if (chan == 0) { 506 start = 0x48000000; 507 size -= 0x8000000; 508 } 509 510 fdtsize = cpu_to_fdt64(size); 511 512 snprintf(nodename, sizeof(nodename), "memory@"); 513 unsigned_num_print(start, 16, nodename + strlen(nodename)); 514 node = ret = fdt_add_subnode(fdt, 0, nodename); 515 if (ret < 0) 516 goto err; 517 518 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 519 if (ret < 0) 520 goto err; 521 522 ret = fdt_setprop_u64(fdt, node, "reg", start); 523 if (ret < 0) 524 goto err; 525 526 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 527 sizeof(fdtsize)); 528 if (ret < 0) 529 goto err; 530 } 531 532 return; 533 err: 534 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 535 panic(); 536 } 537 538 static void bl2_advertise_dram_size(uint32_t product) 539 { 540 uint64_t dram_config[8] = { 541 [0] = 0x400000000ULL, 542 [2] = 0x500000000ULL, 543 [4] = 0x600000000ULL, 544 [6] = 0x700000000ULL, 545 }; 546 547 switch (product) { 548 case RCAR_PRODUCT_H3: 549 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 550 /* 4GB(1GBx4) */ 551 dram_config[1] = 0x40000000ULL; 552 dram_config[3] = 0x40000000ULL; 553 dram_config[5] = 0x40000000ULL; 554 dram_config[7] = 0x40000000ULL; 555 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 556 (RCAR_DRAM_CHANNEL == 5) && \ 557 (RCAR_DRAM_SPLIT == 2) 558 /* 4GB(2GBx2 2ch split) */ 559 dram_config[1] = 0x80000000ULL; 560 dram_config[3] = 0x80000000ULL; 561 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 562 /* 8GB(2GBx4: default) */ 563 dram_config[1] = 0x80000000ULL; 564 dram_config[3] = 0x80000000ULL; 565 dram_config[5] = 0x80000000ULL; 566 dram_config[7] = 0x80000000ULL; 567 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 568 break; 569 570 case RCAR_PRODUCT_M3: 571 #if (RCAR_GEN3_ULCB == 1) 572 /* 2GB(1GBx2 2ch split) */ 573 dram_config[1] = 0x40000000ULL; 574 dram_config[5] = 0x40000000ULL; 575 #else 576 /* 4GB(2GBx2 2ch split) */ 577 dram_config[1] = 0x80000000ULL; 578 dram_config[5] = 0x80000000ULL; 579 #endif 580 break; 581 582 case RCAR_PRODUCT_M3N: 583 /* 2GB(1GBx2) */ 584 dram_config[1] = 0x80000000ULL; 585 break; 586 587 case RCAR_PRODUCT_E3: 588 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 589 /* 1GB(512MBx2) */ 590 dram_config[1] = 0x40000000ULL; 591 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 592 /* 2GB(512MBx4) */ 593 dram_config[1] = 0x80000000ULL; 594 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 595 /* 4GB(1GBx4) */ 596 dram_config[1] = 0x100000000ULL; 597 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 598 break; 599 } 600 601 bl2_advertise_dram_entries(dram_config); 602 } 603 604 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 605 u_register_t arg3, u_register_t arg4) 606 { 607 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 608 uint32_t product, product_cut, major, minor; 609 int32_t ret; 610 const char *str; 611 const char *unknown = "unknown"; 612 const char *cpu_ca57 = "CA57"; 613 const char *cpu_ca53 = "CA53"; 614 const char *product_m3n = "M3N"; 615 const char *product_h3 = "H3"; 616 const char *product_m3 = "M3"; 617 const char *product_e3 = "E3"; 618 const char *lcs_secure = "SE"; 619 const char *lcs_cm = "CM"; 620 const char *lcs_dm = "DM"; 621 const char *lcs_sd = "SD"; 622 const char *lcs_fa = "FA"; 623 const char *sscg_off = "PLL1 nonSSCG Clock select"; 624 const char *sscg_on = "PLL1 SSCG Clock select"; 625 const char *boot_hyper80 = "HyperFlash(80MHz)"; 626 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 627 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 628 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 629 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 630 #if RCAR_LSI == RCAR_E3 631 const char *boot_hyper160 = "HyperFlash(150MHz)"; 632 #else 633 const char *boot_hyper160 = "HyperFlash(160MHz)"; 634 #endif 635 #if (RCAR_LOSSY_ENABLE == 1) 636 int fcnlnode; 637 #endif 638 639 bl2_init_generic_timer(); 640 641 reg = mmio_read_32(RCAR_MODEMR); 642 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 643 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 644 645 bl2_cpg_init(); 646 647 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 648 boot_cpu == MODEMR_BOOT_CPU_CA53) { 649 rcar_pfc_init(); 650 /* console configuration (platform specific) done in driver */ 651 console_init(0, 0, 0); 652 } 653 654 plat_rcar_gic_driver_init(); 655 plat_rcar_gic_init(); 656 rcar_swdt_init(); 657 658 /* FIQ interrupts are taken to EL3 */ 659 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 660 661 write_daifclr(DAIF_FIQ_BIT); 662 663 reg = read_midr(); 664 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 665 switch (midr) { 666 case MIDR_CA57: 667 str = cpu_ca57; 668 break; 669 case MIDR_CA53: 670 str = cpu_ca53; 671 break; 672 default: 673 str = unknown; 674 break; 675 } 676 677 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 678 version_of_renesas); 679 680 reg = mmio_read_32(RCAR_PRR); 681 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 682 product = reg & RCAR_PRODUCT_MASK; 683 684 switch (product) { 685 case RCAR_PRODUCT_H3: 686 str = product_h3; 687 break; 688 case RCAR_PRODUCT_M3: 689 str = product_m3; 690 break; 691 case RCAR_PRODUCT_M3N: 692 str = product_m3n; 693 break; 694 case RCAR_PRODUCT_E3: 695 str = product_e3; 696 break; 697 default: 698 str = unknown; 699 break; 700 } 701 702 if ((RCAR_PRODUCT_M3 == product) && 703 (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) { 704 if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) { 705 /* M3 Ver.1.1 or Ver.1.2 */ 706 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 707 str); 708 } else { 709 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 710 str, 711 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 712 } 713 } else { 714 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 715 major = major + RCAR_MAJOR_OFFSET; 716 minor = reg & RCAR_MINOR_MASK; 717 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 718 } 719 720 if (product == RCAR_PRODUCT_E3) { 721 reg = mmio_read_32(RCAR_MODEMR); 722 sscg = reg & RCAR_SSCG_MASK; 723 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 724 NOTICE("BL2: %s\n", str); 725 } 726 727 rcar_get_board_type(&type, &rev); 728 729 switch (type) { 730 case BOARD_SALVATOR_X: 731 case BOARD_KRIEK: 732 case BOARD_STARTER_KIT: 733 case BOARD_SALVATOR_XS: 734 case BOARD_EBISU: 735 case BOARD_STARTER_KIT_PRE: 736 case BOARD_EBISU_4D: 737 break; 738 default: 739 type = BOARD_UNKNOWN; 740 break; 741 } 742 743 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 744 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 745 else { 746 NOTICE("BL2: Board is %s Rev.%d.%d\n", 747 GET_BOARD_NAME(type), 748 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 749 } 750 751 #if RCAR_LSI != RCAR_AUTO 752 if (product != TARGET_PRODUCT) { 753 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 754 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 755 panic(); 756 } 757 #endif 758 rcar_avs_init(); 759 rcar_avs_setting(); 760 761 switch (boot_dev) { 762 case MODEMR_BOOT_DEV_HYPERFLASH160: 763 str = boot_hyper160; 764 break; 765 case MODEMR_BOOT_DEV_HYPERFLASH80: 766 str = boot_hyper80; 767 break; 768 case MODEMR_BOOT_DEV_QSPI_FLASH40: 769 str = boot_qspi40; 770 break; 771 case MODEMR_BOOT_DEV_QSPI_FLASH80: 772 str = boot_qspi80; 773 break; 774 case MODEMR_BOOT_DEV_EMMC_25X1: 775 str = boot_emmc25x1; 776 break; 777 case MODEMR_BOOT_DEV_EMMC_50X8: 778 str = boot_emmc50x8; 779 break; 780 default: 781 str = unknown; 782 break; 783 } 784 NOTICE("BL2: Boot device is %s\n", str); 785 786 rcar_avs_setting(); 787 reg = rcar_rom_get_lcs(&lcs); 788 if (reg) { 789 str = unknown; 790 goto lcm_state; 791 } 792 793 switch (lcs) { 794 case LCS_CM: 795 str = lcs_cm; 796 break; 797 case LCS_DM: 798 str = lcs_dm; 799 break; 800 case LCS_SD: 801 str = lcs_sd; 802 break; 803 case LCS_SE: 804 str = lcs_secure; 805 break; 806 case LCS_FA: 807 str = lcs_fa; 808 break; 809 default: 810 str = unknown; 811 break; 812 } 813 814 lcm_state: 815 NOTICE("BL2: LCM state is %s\n", str); 816 817 rcar_avs_end(); 818 is_ddr_backup_mode(); 819 820 bl2_tzram_layout.total_base = BL31_BASE; 821 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 822 823 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 824 boot_cpu == MODEMR_BOOT_CPU_CA53) { 825 ret = rcar_dram_init(); 826 if (ret) { 827 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 828 panic(); 829 } 830 rcar_qos_init(); 831 } 832 833 /* Set up FDT */ 834 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 835 if (ret) { 836 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 837 panic(); 838 } 839 840 /* Add platform compatible string */ 841 bl2_populate_compatible_string(fdt); 842 843 /* Print DRAM layout */ 844 bl2_advertise_dram_size(product); 845 846 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 847 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 848 if (rcar_emmc_init() != EMMC_SUCCESS) { 849 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 850 panic(); 851 } 852 rcar_emmc_memcard_power(EMMC_POWER_ON); 853 if (rcar_emmc_mount() != EMMC_SUCCESS) { 854 NOTICE("BL2: Failed to eMMC mount operation.\n"); 855 panic(); 856 } 857 } else { 858 rcar_rpc_init(); 859 rcar_dma_init(); 860 } 861 862 reg = mmio_read_32(RST_WDTRSTCR); 863 reg &= ~WDTRSTCR_RWDT_RSTMSK; 864 reg |= WDTRSTCR_PASSWORD; 865 mmio_write_32(RST_WDTRSTCR, reg); 866 867 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 868 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 869 870 reg = mmio_read_32(RCAR_PRR); 871 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 872 mmio_write_32(CPG_CA57DBGRCR, 873 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 874 875 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 876 mmio_write_32(CPG_CA53DBGRCR, 877 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 878 879 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 880 reg = mmio_read_32(CPG_PLL2CR); 881 reg &= ~((uint32_t) 1 << 5); 882 mmio_write_32(CPG_PLL2CR, reg); 883 884 reg = mmio_read_32(CPG_PLL4CR); 885 reg &= ~((uint32_t) 1 << 5); 886 mmio_write_32(CPG_PLL4CR, reg); 887 888 reg = mmio_read_32(CPG_PLL0CR); 889 reg &= ~((uint32_t) 1 << 12); 890 mmio_write_32(CPG_PLL0CR, reg); 891 } 892 #if (RCAR_LOSSY_ENABLE == 1) 893 NOTICE("BL2: Lossy Decomp areas\n"); 894 895 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 896 if (fcnlnode < 0) { 897 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 898 fcnlnode); 899 panic(); 900 } 901 902 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 903 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 904 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 905 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 906 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 907 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 908 #endif 909 910 fdt_pack(fdt); 911 NOTICE("BL2: FDT at %p\n", fdt); 912 913 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 914 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 915 rcar_io_emmc_setup(); 916 else 917 rcar_io_setup(); 918 } 919 920 void bl2_el3_plat_arch_setup(void) 921 { 922 #if RCAR_BL2_DCACHE == 1 923 NOTICE("BL2: D-Cache enable\n"); 924 rcar_configure_mmu_el3(BL2_BASE, 925 BL2_END - BL2_BASE, 926 BL2_RO_BASE, BL2_RO_LIMIT 927 #if USE_COHERENT_MEM 928 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 929 #endif 930 ); 931 #endif 932 } 933 934 void bl2_platform_setup(void) 935 { 936 937 } 938 939 static void bl2_init_generic_timer(void) 940 { 941 #if RCAR_LSI == RCAR_E3 942 uint32_t reg_cntfid = EXTAL_EBISU; 943 #else /* RCAR_LSI == RCAR_E3 */ 944 uint32_t reg; 945 uint32_t reg_cntfid; 946 uint32_t modemr; 947 uint32_t modemr_pll; 948 uint32_t board_type; 949 uint32_t board_rev; 950 uint32_t pll_table[] = { 951 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 952 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 953 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 954 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 955 }; 956 957 modemr = mmio_read_32(RCAR_MODEMR); 958 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 959 960 /* Set frequency data in CNTFID0 */ 961 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 962 reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 963 switch (modemr_pll) { 964 case MD14_MD13_TYPE_0: 965 rcar_get_board_type(&board_type, &board_rev); 966 if (BOARD_SALVATOR_XS == board_type) { 967 reg_cntfid = EXTAL_SALVATOR_XS; 968 } 969 break; 970 case MD14_MD13_TYPE_3: 971 if (RCAR_PRODUCT_H3_CUT10 == reg) { 972 reg_cntfid = reg_cntfid >> 1U; 973 } 974 break; 975 default: 976 /* none */ 977 break; 978 } 979 #endif /* RCAR_LSI == RCAR_E3 */ 980 /* Update memory mapped and register based freqency */ 981 write_cntfrq_el0((u_register_t )reg_cntfid); 982 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 983 /* Enable counter */ 984 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 985 (uint32_t)CNTCR_EN); 986 } 987