1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <desc_image_load.h> 8 #include <arch_helpers.h> 9 #include <bl_common.h> 10 #include <bl1.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <libfdt.h> 14 #include <mmio.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <string.h> 18 #include <xlat_tables_defs.h> 19 20 #include "avs_driver.h" 21 #include "boot_init_dram.h" 22 #include "cpg_registers.h" 23 #include "board.h" 24 #include "emmc_def.h" 25 #include "emmc_hal.h" 26 #include "emmc_std.h" 27 28 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 29 #include "iic_dvfs.h" 30 #endif 31 32 #include "io_common.h" 33 #include "qos_init.h" 34 #include "rcar_def.h" 35 #include "rcar_private.h" 36 #include "rcar_version.h" 37 #include "rom_api.h" 38 39 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 40 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 41 42 #if USE_COHERENT_MEM 43 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 44 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 45 #endif 46 47 extern void plat_rcar_gic_driver_init(void); 48 extern void plat_rcar_gic_init(void); 49 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 50 extern void bl2_system_cpg_init(void); 51 extern void bl2_secure_setting(void); 52 extern void bl2_cpg_init(void); 53 extern void rcar_io_emmc_setup(void); 54 extern void rcar_io_setup(void); 55 extern void rcar_swdt_release(void); 56 extern void rcar_swdt_init(void); 57 extern void rcar_rpc_init(void); 58 extern void rcar_pfc_init(void); 59 extern void rcar_dma_init(void); 60 61 /* R-Car Gen3 product check */ 62 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 63 #define TARGET_PRODUCT RCAR_PRODUCT_H3 64 #define TARGET_NAME "R-Car H3" 65 #elif RCAR_LSI == RCAR_M3 66 #define TARGET_PRODUCT RCAR_PRODUCT_M3 67 #define TARGET_NAME "R-Car M3" 68 #elif RCAR_LSI == RCAR_M3N 69 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 70 #define TARGET_NAME "R-Car M3N" 71 #elif RCAR_LSI == RCAR_E3 72 #define TARGET_PRODUCT RCAR_PRODUCT_E3 73 #define TARGET_NAME "R-Car E3" 74 #endif 75 76 #if (RCAR_LSI == RCAR_E3) 77 #define GPIO_INDT (GPIO_INDT6) 78 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 79 #else 80 #define GPIO_INDT (GPIO_INDT1) 81 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 82 #endif 83 84 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 85 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 86 assert_bl31_params_do_not_fit_in_shared_memory); 87 88 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 89 90 /* FDT with DRAM configuration */ 91 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 92 static void *fdt = (void *)fdt_blob; 93 94 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 95 char *string) 96 { 97 /* Just need enough space to store 64 bit decimal integer */ 98 char num_buf[20]; 99 int i = 0; 100 unsigned int rem; 101 102 do { 103 rem = unum % radix; 104 if (rem < 0xa) 105 num_buf[i] = '0' + rem; 106 else 107 num_buf[i] = 'a' + (rem - 0xa); 108 i++; 109 unum /= radix; 110 } while (unum > 0U); 111 112 while (--i >= 0) 113 *string++ = num_buf[i]; 114 } 115 116 #if (RCAR_LOSSY_ENABLE == 1) 117 typedef struct bl2_lossy_info { 118 uint32_t magic; 119 uint32_t a0; 120 uint32_t b0; 121 } bl2_lossy_info_t; 122 123 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 124 uint64_t end_addr, uint32_t format, 125 uint32_t enable, int fcnlnode) 126 { 127 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 128 char nodename[40] = { 0 }; 129 int ret, node; 130 131 /* Ignore undefined addresses */ 132 if (start_addr == 0 && end_addr == 0) 133 return; 134 135 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 136 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 137 138 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 139 if (ret < 0) { 140 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 141 panic(); 142 } 143 144 ret = fdt_setprop_string(fdt, node, "compatible", 145 "renesas,lossy-decompression"); 146 if (ret < 0) { 147 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 148 panic(); 149 } 150 151 ret = fdt_appendprop_string(fdt, node, "compatible", 152 "shared-dma-pool"); 153 if (ret < 0) { 154 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 155 panic(); 156 } 157 158 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 159 if (ret < 0) { 160 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 161 panic(); 162 } 163 164 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 165 if (ret < 0) { 166 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 167 panic(); 168 } 169 170 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 171 if (ret < 0) { 172 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 173 panic(); 174 } 175 176 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 177 if (ret < 0) { 178 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 179 panic(); 180 } 181 } 182 183 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 184 uint64_t end_addr, uint32_t format, 185 uint32_t enable, int fcnlnode) 186 { 187 bl2_lossy_info_t info; 188 uint32_t reg; 189 190 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 191 192 reg = format | (start_addr >> 20); 193 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 194 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 195 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 196 197 info.magic = 0x12345678U; 198 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 199 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 200 201 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 202 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 203 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 204 205 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 206 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 207 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 208 } 209 #endif 210 211 void bl2_plat_flush_bl31_params(void) 212 { 213 uint32_t product_cut, product, cut; 214 uint32_t boot_dev, boot_cpu; 215 uint32_t lcs, reg, val; 216 217 reg = mmio_read_32(RCAR_MODEMR); 218 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 219 220 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 221 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 222 emmc_terminate(); 223 224 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 225 bl2_secure_setting(); 226 227 reg = mmio_read_32(RCAR_PRR); 228 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 229 product = reg & RCAR_PRODUCT_MASK; 230 cut = reg & RCAR_CUT_MASK; 231 232 if (product == RCAR_PRODUCT_M3) 233 goto tlb; 234 235 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 236 goto tlb; 237 238 /* Disable MFIS write protection */ 239 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 240 241 tlb: 242 reg = mmio_read_32(RCAR_MODEMR); 243 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 244 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 245 boot_cpu != MODEMR_BOOT_CPU_CA53) 246 goto mmu; 247 248 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 249 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 250 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 251 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 252 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 253 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 254 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 255 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 256 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 257 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 258 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 259 } else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 260 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 261 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 262 } 263 264 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 265 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 266 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 267 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 268 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 269 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 270 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 271 272 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 273 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 274 } 275 276 mmu: 277 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 278 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 279 280 val = rcar_rom_get_lcs(&lcs); 281 if (val) { 282 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 283 panic(); 284 } 285 286 if (lcs == LCS_SE) 287 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 288 289 rcar_swdt_release(); 290 bl2_system_cpg_init(); 291 292 #if RCAR_BL2_DCACHE == 1 293 /* Disable data cache (clean and invalidate) */ 294 disable_mmu_el3(); 295 #endif 296 } 297 298 static uint32_t is_ddr_backup_mode(void) 299 { 300 #if RCAR_SYSTEM_SUSPEND 301 static uint32_t reason = RCAR_COLD_BOOT; 302 static uint32_t once; 303 304 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 305 uint8_t data; 306 #endif 307 if (once) 308 return reason; 309 310 once = 1; 311 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 312 return reason; 313 314 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 315 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 316 ERROR("BL2: REG Keep10 READ ERROR.\n"); 317 panic(); 318 } 319 320 if (KEEP10_MAGIC != data) 321 reason = RCAR_WARM_BOOT; 322 #else 323 reason = RCAR_WARM_BOOT; 324 #endif 325 return reason; 326 #else 327 return RCAR_COLD_BOOT; 328 #endif 329 } 330 331 int bl2_plat_handle_pre_image_load(unsigned int image_id) 332 { 333 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 334 bl_mem_params_node_t *bl_mem_params; 335 336 if (image_id != BL31_IMAGE_ID) 337 return 0; 338 339 bl_mem_params = get_bl_mem_params_node(image_id); 340 341 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 342 goto cold_boot; 343 344 *boot_kind = RCAR_WARM_BOOT; 345 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 346 347 console_flush(); 348 bl2_plat_flush_bl31_params(); 349 350 /* will not return */ 351 bl2_enter_bl31(&bl_mem_params->ep_info); 352 353 cold_boot: 354 *boot_kind = RCAR_COLD_BOOT; 355 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 356 357 return 0; 358 } 359 360 int bl2_plat_handle_post_image_load(unsigned int image_id) 361 { 362 static bl2_to_bl31_params_mem_t *params; 363 bl_mem_params_node_t *bl_mem_params; 364 365 if (!params) { 366 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 367 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 368 } 369 370 bl_mem_params = get_bl_mem_params_node(image_id); 371 372 switch (image_id) { 373 case BL31_IMAGE_ID: 374 break; 375 case BL32_IMAGE_ID: 376 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 377 sizeof(entry_point_info_t)); 378 break; 379 case BL33_IMAGE_ID: 380 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 381 sizeof(entry_point_info_t)); 382 break; 383 } 384 385 return 0; 386 } 387 388 meminfo_t *bl2_plat_sec_mem_layout(void) 389 { 390 return &bl2_tzram_layout; 391 } 392 393 static void bl2_populate_compatible_string(void *fdt) 394 { 395 uint32_t board_type; 396 uint32_t board_rev; 397 uint32_t reg; 398 int ret; 399 400 /* Populate compatible string */ 401 rcar_get_board_type(&board_type, &board_rev); 402 switch (board_type) { 403 case BOARD_SALVATOR_X: 404 ret = fdt_setprop_string(fdt, 0, "compatible", 405 "renesas,salvator-x"); 406 break; 407 case BOARD_SALVATOR_XS: 408 ret = fdt_setprop_string(fdt, 0, "compatible", 409 "renesas,salvator-xs"); 410 break; 411 case BOARD_STARTER_KIT: 412 ret = fdt_setprop_string(fdt, 0, "compatible", 413 "renesas,m3ulcb"); 414 break; 415 case BOARD_STARTER_KIT_PRE: 416 ret = fdt_setprop_string(fdt, 0, "compatible", 417 "renesas,h3ulcb"); 418 break; 419 case BOARD_EBISU: 420 case BOARD_EBISU_4D: 421 ret = fdt_setprop_string(fdt, 0, "compatible", 422 "renesas,ebisu"); 423 break; 424 default: 425 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 426 panic(); 427 } 428 429 if (ret < 0) { 430 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 431 panic(); 432 } 433 434 reg = mmio_read_32(RCAR_PRR); 435 switch (reg & RCAR_PRODUCT_MASK) { 436 case RCAR_PRODUCT_H3: 437 ret = fdt_appendprop_string(fdt, 0, "compatible", 438 "renesas,r8a7795"); 439 break; 440 case RCAR_PRODUCT_M3: 441 ret = fdt_appendprop_string(fdt, 0, "compatible", 442 "renesas,r8a7796"); 443 break; 444 case RCAR_PRODUCT_M3N: 445 ret = fdt_appendprop_string(fdt, 0, "compatible", 446 "renesas,r8a77965"); 447 break; 448 case RCAR_PRODUCT_E3: 449 ret = fdt_appendprop_string(fdt, 0, "compatible", 450 "renesas,r8a77990"); 451 break; 452 default: 453 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 454 panic(); 455 } 456 457 if (ret < 0) { 458 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 459 panic(); 460 } 461 } 462 463 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 464 { 465 char nodename[32] = { 0 }; 466 uint64_t start, size; 467 uint64_t fdtsize; 468 int ret, node, chan; 469 470 for (chan = 0; chan < 4; chan++) { 471 start = dram_config[2 * chan]; 472 size = dram_config[2 * chan + 1]; 473 if (!size) 474 continue; 475 476 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 477 chan, start, start + size - 1, size >> 30); 478 } 479 480 /* 481 * We add the DT nodes in reverse order here. The fdt_add_subnode() 482 * adds the DT node before the first existing DT node, so we have 483 * to add them in reverse order to get nodes sorted by address in 484 * the resulting DT. 485 */ 486 for (chan = 3; chan >= 0; chan--) { 487 start = dram_config[2 * chan]; 488 size = dram_config[2 * chan + 1]; 489 if (!size) 490 continue; 491 492 /* 493 * Channel 0 is mapped in 32bit space and the first 494 * 128 MiB are reserved 495 */ 496 if (chan == 0) { 497 start = 0x48000000; 498 size -= 0x8000000; 499 } 500 501 fdtsize = cpu_to_fdt64(size); 502 503 snprintf(nodename, sizeof(nodename), "memory@"); 504 unsigned_num_print(start, 16, nodename + strlen(nodename)); 505 node = ret = fdt_add_subnode(fdt, 0, nodename); 506 if (ret < 0) 507 goto err; 508 509 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 510 if (ret < 0) 511 goto err; 512 513 ret = fdt_setprop_u64(fdt, node, "reg", start); 514 if (ret < 0) 515 goto err; 516 517 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 518 sizeof(fdtsize)); 519 if (ret < 0) 520 goto err; 521 } 522 523 return; 524 err: 525 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 526 panic(); 527 } 528 529 static void bl2_advertise_dram_size(uint32_t product) 530 { 531 uint64_t dram_config[8] = { 532 [0] = 0x400000000ULL, 533 [2] = 0x500000000ULL, 534 [4] = 0x600000000ULL, 535 [6] = 0x700000000ULL, 536 }; 537 538 switch (product) { 539 case RCAR_PRODUCT_H3: 540 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 541 /* 4GB(1GBx4) */ 542 dram_config[1] = 0x40000000ULL; 543 dram_config[3] = 0x40000000ULL; 544 dram_config[5] = 0x40000000ULL; 545 dram_config[7] = 0x40000000ULL; 546 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 547 (RCAR_DRAM_CHANNEL == 5) && \ 548 (RCAR_DRAM_SPLIT == 2) 549 /* 4GB(2GBx2 2ch split) */ 550 dram_config[1] = 0x80000000ULL; 551 dram_config[3] = 0x80000000ULL; 552 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 553 /* 8GB(2GBx4: default) */ 554 dram_config[1] = 0x80000000ULL; 555 dram_config[3] = 0x80000000ULL; 556 dram_config[5] = 0x80000000ULL; 557 dram_config[7] = 0x80000000ULL; 558 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 559 break; 560 561 case RCAR_PRODUCT_M3: 562 /* 4GB(2GBx2 2ch split) */ 563 dram_config[1] = 0x80000000ULL; 564 dram_config[5] = 0x80000000ULL; 565 break; 566 567 case RCAR_PRODUCT_M3N: 568 /* 2GB(1GBx2) */ 569 dram_config[1] = 0x80000000ULL; 570 break; 571 572 case RCAR_PRODUCT_E3: 573 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 574 /* 1GB(512MBx2) */ 575 dram_config[1] = 0x40000000ULL; 576 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 577 /* 2GB(512MBx4) */ 578 dram_config[1] = 0x80000000ULL; 579 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 580 /* 4GB(1GBx4) */ 581 dram_config[1] = 0x100000000ULL; 582 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 583 break; 584 } 585 586 bl2_advertise_dram_entries(dram_config); 587 } 588 589 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 590 u_register_t arg3, u_register_t arg4) 591 { 592 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 593 uint32_t product, product_cut, major, minor; 594 int32_t ret; 595 const char *str; 596 const char *unknown = "unknown"; 597 const char *cpu_ca57 = "CA57"; 598 const char *cpu_ca53 = "CA53"; 599 const char *product_m3n = "M3N"; 600 const char *product_h3 = "H3"; 601 const char *product_m3 = "M3"; 602 const char *product_e3 = "E3"; 603 const char *lcs_secure = "SE"; 604 const char *lcs_cm = "CM"; 605 const char *lcs_dm = "DM"; 606 const char *lcs_sd = "SD"; 607 const char *lcs_fa = "FA"; 608 const char *sscg_off = "PLL1 nonSSCG Clock select"; 609 const char *sscg_on = "PLL1 SSCG Clock select"; 610 const char *boot_hyper80 = "HyperFlash(80MHz)"; 611 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 612 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 613 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 614 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 615 #if RCAR_LSI == RCAR_E3 616 const char *boot_hyper160 = "HyperFlash(150MHz)"; 617 #else 618 const char *boot_hyper160 = "HyperFlash(160MHz)"; 619 #endif 620 #if (RCAR_LOSSY_ENABLE == 1) 621 int fcnlnode; 622 #endif 623 624 reg = mmio_read_32(RCAR_MODEMR); 625 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 626 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 627 628 bl2_cpg_init(); 629 630 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 631 boot_cpu == MODEMR_BOOT_CPU_CA53) { 632 rcar_pfc_init(); 633 /* console configuration (platform specific) done in driver */ 634 console_init(0, 0, 0); 635 } 636 637 plat_rcar_gic_driver_init(); 638 plat_rcar_gic_init(); 639 rcar_swdt_init(); 640 641 /* FIQ interrupts are taken to EL3 */ 642 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 643 644 write_daifclr(DAIF_FIQ_BIT); 645 646 reg = read_midr(); 647 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 648 switch (midr) { 649 case MIDR_CA57: 650 str = cpu_ca57; 651 break; 652 case MIDR_CA53: 653 str = cpu_ca53; 654 break; 655 default: 656 str = unknown; 657 break; 658 } 659 660 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 661 version_of_renesas); 662 663 reg = mmio_read_32(RCAR_PRR); 664 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 665 product = reg & RCAR_PRODUCT_MASK; 666 667 switch (product) { 668 case RCAR_PRODUCT_H3: 669 str = product_h3; 670 break; 671 case RCAR_PRODUCT_M3: 672 str = product_m3; 673 break; 674 case RCAR_PRODUCT_M3N: 675 str = product_m3n; 676 break; 677 case RCAR_PRODUCT_E3: 678 str = product_e3; 679 break; 680 default: 681 str = unknown; 682 break; 683 } 684 685 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 686 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 687 } else { 688 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 689 major = major + RCAR_MAJOR_OFFSET; 690 minor = reg & RCAR_MINOR_MASK; 691 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 692 } 693 694 if (product == RCAR_PRODUCT_E3) { 695 reg = mmio_read_32(RCAR_MODEMR); 696 sscg = reg & RCAR_SSCG_MASK; 697 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 698 NOTICE("BL2: %s\n", str); 699 } 700 701 rcar_get_board_type(&type, &rev); 702 703 switch (type) { 704 case BOARD_SALVATOR_X: 705 case BOARD_KRIEK: 706 case BOARD_STARTER_KIT: 707 case BOARD_SALVATOR_XS: 708 case BOARD_EBISU: 709 case BOARD_STARTER_KIT_PRE: 710 case BOARD_EBISU_4D: 711 break; 712 default: 713 type = BOARD_UNKNOWN; 714 break; 715 } 716 717 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 718 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 719 else { 720 NOTICE("BL2: Board is %s Rev.%d.%d\n", 721 GET_BOARD_NAME(type), 722 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 723 } 724 725 #if RCAR_LSI != RCAR_AUTO 726 if (product != TARGET_PRODUCT) { 727 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 728 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 729 panic(); 730 } 731 #endif 732 rcar_avs_init(); 733 rcar_avs_setting(); 734 735 switch (boot_dev) { 736 case MODEMR_BOOT_DEV_HYPERFLASH160: 737 str = boot_hyper160; 738 break; 739 case MODEMR_BOOT_DEV_HYPERFLASH80: 740 str = boot_hyper80; 741 break; 742 case MODEMR_BOOT_DEV_QSPI_FLASH40: 743 str = boot_qspi40; 744 break; 745 case MODEMR_BOOT_DEV_QSPI_FLASH80: 746 str = boot_qspi80; 747 break; 748 case MODEMR_BOOT_DEV_EMMC_25X1: 749 str = boot_emmc25x1; 750 break; 751 case MODEMR_BOOT_DEV_EMMC_50X8: 752 str = boot_emmc50x8; 753 break; 754 default: 755 str = unknown; 756 break; 757 } 758 NOTICE("BL2: Boot device is %s\n", str); 759 760 rcar_avs_setting(); 761 reg = rcar_rom_get_lcs(&lcs); 762 if (reg) { 763 str = unknown; 764 goto lcm_state; 765 } 766 767 switch (lcs) { 768 case LCS_CM: 769 str = lcs_cm; 770 break; 771 case LCS_DM: 772 str = lcs_dm; 773 break; 774 case LCS_SD: 775 str = lcs_sd; 776 break; 777 case LCS_SE: 778 str = lcs_secure; 779 break; 780 case LCS_FA: 781 str = lcs_fa; 782 break; 783 default: 784 str = unknown; 785 break; 786 } 787 788 lcm_state: 789 NOTICE("BL2: LCM state is %s\n", str); 790 791 rcar_avs_end(); 792 is_ddr_backup_mode(); 793 794 bl2_tzram_layout.total_base = BL31_BASE; 795 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 796 797 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 798 boot_cpu == MODEMR_BOOT_CPU_CA53) { 799 ret = rcar_dram_init(); 800 if (ret) { 801 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 802 panic(); 803 } 804 rcar_qos_init(); 805 } 806 807 /* Set up FDT */ 808 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 809 if (ret) { 810 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 811 panic(); 812 } 813 814 /* Add platform compatible string */ 815 bl2_populate_compatible_string(fdt); 816 817 /* Print DRAM layout */ 818 bl2_advertise_dram_size(product); 819 820 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 821 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 822 if (rcar_emmc_init() != EMMC_SUCCESS) { 823 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 824 panic(); 825 } 826 rcar_emmc_memcard_power(EMMC_POWER_ON); 827 if (rcar_emmc_mount() != EMMC_SUCCESS) { 828 NOTICE("BL2: Failed to eMMC mount operation.\n"); 829 panic(); 830 } 831 } else { 832 rcar_rpc_init(); 833 rcar_dma_init(); 834 } 835 836 reg = mmio_read_32(RST_WDTRSTCR); 837 reg &= ~WDTRSTCR_RWDT_RSTMSK; 838 reg |= WDTRSTCR_PASSWORD; 839 mmio_write_32(RST_WDTRSTCR, reg); 840 841 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 842 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 843 844 reg = mmio_read_32(RCAR_PRR); 845 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 846 mmio_write_32(CPG_CA57DBGRCR, 847 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 848 849 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 850 mmio_write_32(CPG_CA53DBGRCR, 851 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 852 853 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 854 reg = mmio_read_32(CPG_PLL2CR); 855 reg &= ~((uint32_t) 1 << 5); 856 mmio_write_32(CPG_PLL2CR, reg); 857 858 reg = mmio_read_32(CPG_PLL4CR); 859 reg &= ~((uint32_t) 1 << 5); 860 mmio_write_32(CPG_PLL4CR, reg); 861 862 reg = mmio_read_32(CPG_PLL0CR); 863 reg &= ~((uint32_t) 1 << 12); 864 mmio_write_32(CPG_PLL0CR, reg); 865 } 866 #if (RCAR_LOSSY_ENABLE == 1) 867 NOTICE("BL2: Lossy Decomp areas\n"); 868 869 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 870 if (fcnlnode < 0) { 871 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 872 fcnlnode); 873 panic(); 874 } 875 876 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 877 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 878 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 879 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 880 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 881 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 882 #endif 883 884 fdt_pack(fdt); 885 NOTICE("BL2: FDT at %p\n", fdt); 886 887 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 888 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 889 rcar_io_emmc_setup(); 890 else 891 rcar_io_setup(); 892 } 893 894 void bl2_el3_plat_arch_setup(void) 895 { 896 #if RCAR_BL2_DCACHE == 1 897 NOTICE("BL2: D-Cache enable\n"); 898 rcar_configure_mmu_el3(BL2_BASE, 899 RCAR_SYSRAM_LIMIT - BL2_BASE, 900 BL2_RO_BASE, BL2_RO_LIMIT 901 #if USE_COHERENT_MEM 902 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 903 #endif 904 ); 905 #endif 906 } 907 908 void bl2_platform_setup(void) 909 { 910 911 } 912