1 /* 2 * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <drivers/io/io_driver.h> 20 #include <drivers/io/io_storage.h> 21 #include <lib/mmio.h> 22 #include <lib/xlat_tables/xlat_tables_defs.h> 23 #include <plat/common/platform.h> 24 25 #include "avs_driver.h" 26 #include "boot_init_dram.h" 27 #include "cpg_registers.h" 28 #include "board.h" 29 #include "emmc_def.h" 30 #include "emmc_hal.h" 31 #include "emmc_std.h" 32 33 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 34 #include "iic_dvfs.h" 35 #endif 36 37 #include "io_common.h" 38 #include "io_rcar.h" 39 #include "qos_init.h" 40 #include "rcar_def.h" 41 #include "rcar_private.h" 42 #include "rcar_version.h" 43 #include "rom_api.h" 44 45 #if RCAR_BL2_DCACHE == 1 46 /* 47 * Following symbols are only used during plat_arch_setup() only 48 * when RCAR_BL2_DCACHE is enabled. 49 */ 50 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 51 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 52 53 #if USE_COHERENT_MEM 54 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 55 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 56 #endif 57 58 #endif 59 60 extern void plat_rcar_gic_driver_init(void); 61 extern void plat_rcar_gic_init(void); 62 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 63 extern void bl2_system_cpg_init(void); 64 extern void bl2_secure_setting(void); 65 extern void bl2_cpg_init(void); 66 extern void rcar_io_emmc_setup(void); 67 extern void rcar_io_setup(void); 68 extern void rcar_swdt_release(void); 69 extern void rcar_swdt_init(void); 70 extern void rcar_rpc_init(void); 71 extern void rcar_pfc_init(void); 72 extern void rcar_dma_init(void); 73 74 static void bl2_init_generic_timer(void); 75 76 /* R-Car Gen3 product check */ 77 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 78 #define TARGET_PRODUCT PRR_PRODUCT_H3 79 #define TARGET_NAME "R-Car H3" 80 #elif RCAR_LSI == RCAR_M3 81 #define TARGET_PRODUCT PRR_PRODUCT_M3 82 #define TARGET_NAME "R-Car M3" 83 #elif RCAR_LSI == RCAR_M3N 84 #define TARGET_PRODUCT PRR_PRODUCT_M3N 85 #define TARGET_NAME "R-Car M3N" 86 #elif RCAR_LSI == RCAR_V3M 87 #define TARGET_PRODUCT PRR_PRODUCT_V3M 88 #define TARGET_NAME "R-Car V3M" 89 #elif RCAR_LSI == RCAR_E3 90 #define TARGET_PRODUCT PRR_PRODUCT_E3 91 #define TARGET_NAME "R-Car E3" 92 #elif RCAR_LSI == RCAR_D3 93 #define TARGET_PRODUCT PRR_PRODUCT_D3 94 #define TARGET_NAME "R-Car D3" 95 #elif RCAR_LSI == RCAR_AUTO 96 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 97 #endif 98 99 #if (RCAR_LSI == RCAR_E3) 100 #define GPIO_INDT (GPIO_INDT6) 101 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 102 #else 103 #define GPIO_INDT (GPIO_INDT1) 104 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 105 #endif 106 107 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 108 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 109 assert_bl31_params_do_not_fit_in_shared_memory); 110 111 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 112 113 /* FDT with DRAM configuration */ 114 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 115 static void *fdt = (void *)fdt_blob; 116 117 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 118 char *string) 119 { 120 /* Just need enough space to store 64 bit decimal integer */ 121 char num_buf[20]; 122 int i = 0; 123 unsigned int rem; 124 125 do { 126 rem = unum % radix; 127 if (rem < 0xa) 128 num_buf[i] = '0' + rem; 129 else 130 num_buf[i] = 'a' + (rem - 0xa); 131 i++; 132 unum /= radix; 133 } while (unum > 0U); 134 135 while (--i >= 0) 136 *string++ = num_buf[i]; 137 } 138 139 #if (RCAR_LOSSY_ENABLE == 1) 140 typedef struct bl2_lossy_info { 141 uint32_t magic; 142 uint32_t a0; 143 uint32_t b0; 144 } bl2_lossy_info_t; 145 146 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 147 uint64_t end_addr, uint32_t format, 148 uint32_t enable, int fcnlnode) 149 { 150 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 151 char nodename[40] = { 0 }; 152 int ret, node; 153 154 /* Ignore undefined addresses */ 155 if (start_addr == 0 && end_addr == 0) 156 return; 157 158 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 159 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 160 161 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 162 if (ret < 0) { 163 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 164 panic(); 165 } 166 167 ret = fdt_setprop_string(fdt, node, "compatible", 168 "renesas,lossy-decompression"); 169 if (ret < 0) { 170 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 171 panic(); 172 } 173 174 ret = fdt_appendprop_string(fdt, node, "compatible", 175 "shared-dma-pool"); 176 if (ret < 0) { 177 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 178 panic(); 179 } 180 181 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 182 if (ret < 0) { 183 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 184 panic(); 185 } 186 187 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 188 if (ret < 0) { 189 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 190 panic(); 191 } 192 193 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 194 if (ret < 0) { 195 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 196 panic(); 197 } 198 199 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 200 if (ret < 0) { 201 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 202 panic(); 203 } 204 } 205 206 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 207 uint64_t end_addr, uint32_t format, 208 uint32_t enable, int fcnlnode) 209 { 210 bl2_lossy_info_t info; 211 uint32_t reg; 212 213 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 214 215 reg = format | (start_addr >> 20); 216 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 217 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 218 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 219 220 info.magic = 0x12345678U; 221 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 222 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 223 224 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 225 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 226 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 227 228 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 229 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 230 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 231 } 232 #endif 233 234 void bl2_plat_flush_bl31_params(void) 235 { 236 uint32_t product_cut, product, cut; 237 uint32_t boot_dev, boot_cpu; 238 uint32_t lcs, reg, val; 239 240 reg = mmio_read_32(RCAR_MODEMR); 241 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 242 243 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 244 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 245 emmc_terminate(); 246 247 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 248 bl2_secure_setting(); 249 250 reg = mmio_read_32(RCAR_PRR); 251 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 252 product = reg & PRR_PRODUCT_MASK; 253 cut = reg & PRR_CUT_MASK; 254 255 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 256 goto tlb; 257 258 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 259 goto tlb; 260 261 if (product == PRR_PRODUCT_D3) 262 goto tlb; 263 264 /* Disable MFIS write protection */ 265 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 266 267 tlb: 268 reg = mmio_read_32(RCAR_MODEMR); 269 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 270 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 271 boot_cpu != MODEMR_BOOT_CPU_CA53) 272 goto mmu; 273 274 if (product_cut == PRR_PRODUCT_H3_CUT20) { 275 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 276 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 277 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 278 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 280 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 281 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 282 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 283 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 284 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 285 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 286 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 287 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 288 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 289 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 290 } 291 292 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 293 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 294 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 295 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 296 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 297 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 298 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 299 300 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 301 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 302 } 303 304 mmu: 305 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 306 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 307 308 val = rcar_rom_get_lcs(&lcs); 309 if (val) { 310 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 311 panic(); 312 } 313 314 if (lcs == LCS_SE) 315 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 316 317 rcar_swdt_release(); 318 bl2_system_cpg_init(); 319 320 #if RCAR_BL2_DCACHE == 1 321 /* Disable data cache (clean and invalidate) */ 322 disable_mmu_el3(); 323 #endif 324 } 325 326 static uint32_t is_ddr_backup_mode(void) 327 { 328 #if RCAR_SYSTEM_SUSPEND 329 static uint32_t reason = RCAR_COLD_BOOT; 330 static uint32_t once; 331 332 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 333 uint8_t data; 334 #endif 335 if (once) 336 return reason; 337 338 once = 1; 339 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 340 return reason; 341 342 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 343 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 344 ERROR("BL2: REG Keep10 READ ERROR.\n"); 345 panic(); 346 } 347 348 if (KEEP10_MAGIC != data) 349 reason = RCAR_WARM_BOOT; 350 #else 351 reason = RCAR_WARM_BOOT; 352 #endif 353 return reason; 354 #else 355 return RCAR_COLD_BOOT; 356 #endif 357 } 358 359 int bl2_plat_handle_pre_image_load(unsigned int image_id) 360 { 361 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 362 bl_mem_params_node_t *bl_mem_params; 363 364 if (image_id != BL31_IMAGE_ID) 365 return 0; 366 367 bl_mem_params = get_bl_mem_params_node(image_id); 368 369 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 370 goto cold_boot; 371 372 *boot_kind = RCAR_WARM_BOOT; 373 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 374 375 console_flush(); 376 bl2_plat_flush_bl31_params(); 377 378 /* will not return */ 379 bl2_enter_bl31(&bl_mem_params->ep_info); 380 381 cold_boot: 382 *boot_kind = RCAR_COLD_BOOT; 383 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 384 385 return 0; 386 } 387 388 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 389 { 390 uint32_t cert, len; 391 int ret; 392 393 ret = rcar_get_certificate(certid, &cert); 394 if (ret) { 395 ERROR("%s : cert file load error", __func__); 396 return 1; 397 } 398 399 rcar_read_certificate((uint64_t) cert, &len, dest); 400 401 return 0; 402 } 403 404 int bl2_plat_handle_post_image_load(unsigned int image_id) 405 { 406 static bl2_to_bl31_params_mem_t *params; 407 bl_mem_params_node_t *bl_mem_params; 408 uintptr_t dest; 409 int ret; 410 411 if (!params) { 412 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 413 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 414 } 415 416 bl_mem_params = get_bl_mem_params_node(image_id); 417 418 switch (image_id) { 419 case BL31_IMAGE_ID: 420 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 421 &dest); 422 if (!ret) 423 bl_mem_params->image_info.image_base = dest; 424 break; 425 case BL32_IMAGE_ID: 426 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 427 &dest); 428 if (!ret) 429 bl_mem_params->image_info.image_base = dest; 430 431 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 432 sizeof(entry_point_info_t)); 433 break; 434 case BL33_IMAGE_ID: 435 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 436 sizeof(entry_point_info_t)); 437 break; 438 } 439 440 return 0; 441 } 442 443 struct meminfo *bl2_plat_sec_mem_layout(void) 444 { 445 return &bl2_tzram_layout; 446 } 447 448 static void bl2_populate_compatible_string(void *dt) 449 { 450 uint32_t board_type; 451 uint32_t board_rev; 452 uint32_t reg; 453 int ret; 454 455 fdt_setprop_u32(dt, 0, "#address-cells", 2); 456 fdt_setprop_u32(dt, 0, "#size-cells", 2); 457 458 /* Populate compatible string */ 459 rcar_get_board_type(&board_type, &board_rev); 460 switch (board_type) { 461 case BOARD_SALVATOR_X: 462 ret = fdt_setprop_string(dt, 0, "compatible", 463 "renesas,salvator-x"); 464 break; 465 case BOARD_SALVATOR_XS: 466 ret = fdt_setprop_string(dt, 0, "compatible", 467 "renesas,salvator-xs"); 468 break; 469 case BOARD_STARTER_KIT: 470 ret = fdt_setprop_string(dt, 0, "compatible", 471 "renesas,m3ulcb"); 472 break; 473 case BOARD_STARTER_KIT_PRE: 474 ret = fdt_setprop_string(dt, 0, "compatible", 475 "renesas,h3ulcb"); 476 break; 477 case BOARD_EAGLE: 478 ret = fdt_setprop_string(dt, 0, "compatible", 479 "renesas,eagle"); 480 break; 481 case BOARD_EBISU: 482 case BOARD_EBISU_4D: 483 ret = fdt_setprop_string(dt, 0, "compatible", 484 "renesas,ebisu"); 485 break; 486 case BOARD_DRAAK: 487 ret = fdt_setprop_string(dt, 0, "compatible", 488 "renesas,draak"); 489 break; 490 default: 491 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 492 panic(); 493 } 494 495 if (ret < 0) { 496 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 497 panic(); 498 } 499 500 reg = mmio_read_32(RCAR_PRR); 501 switch (reg & PRR_PRODUCT_MASK) { 502 case PRR_PRODUCT_H3: 503 ret = fdt_appendprop_string(dt, 0, "compatible", 504 "renesas,r8a7795"); 505 break; 506 case PRR_PRODUCT_M3: 507 ret = fdt_appendprop_string(dt, 0, "compatible", 508 "renesas,r8a7796"); 509 break; 510 case PRR_PRODUCT_M3N: 511 ret = fdt_appendprop_string(dt, 0, "compatible", 512 "renesas,r8a77965"); 513 break; 514 case PRR_PRODUCT_V3M: 515 ret = fdt_appendprop_string(dt, 0, "compatible", 516 "renesas,r8a77970"); 517 break; 518 case PRR_PRODUCT_E3: 519 ret = fdt_appendprop_string(dt, 0, "compatible", 520 "renesas,r8a77990"); 521 break; 522 case PRR_PRODUCT_D3: 523 ret = fdt_appendprop_string(dt, 0, "compatible", 524 "renesas,r8a77995"); 525 break; 526 default: 527 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 528 panic(); 529 } 530 531 if (ret < 0) { 532 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 533 panic(); 534 } 535 } 536 537 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 538 { 539 char nodename[32] = { 0 }; 540 uint64_t start, size; 541 uint64_t fdtsize; 542 int ret, node, chan; 543 544 for (chan = 0; chan < 4; chan++) { 545 start = dram_config[2 * chan]; 546 size = dram_config[2 * chan + 1]; 547 if (!size) 548 continue; 549 550 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 551 chan, start, start + size - 1, 552 (size >> 30) ? : size >> 20, 553 (size >> 30) ? "G" : "M"); 554 } 555 556 /* 557 * We add the DT nodes in reverse order here. The fdt_add_subnode() 558 * adds the DT node before the first existing DT node, so we have 559 * to add them in reverse order to get nodes sorted by address in 560 * the resulting DT. 561 */ 562 for (chan = 3; chan >= 0; chan--) { 563 start = dram_config[2 * chan]; 564 size = dram_config[2 * chan + 1]; 565 if (!size) 566 continue; 567 568 /* 569 * Channel 0 is mapped in 32bit space and the first 570 * 128 MiB are reserved 571 */ 572 if (chan == 0) { 573 start = 0x48000000; 574 size -= 0x8000000; 575 } 576 577 fdtsize = cpu_to_fdt64(size); 578 579 snprintf(nodename, sizeof(nodename), "memory@"); 580 unsigned_num_print(start, 16, nodename + strlen(nodename)); 581 node = ret = fdt_add_subnode(fdt, 0, nodename); 582 if (ret < 0) 583 goto err; 584 585 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 586 if (ret < 0) 587 goto err; 588 589 ret = fdt_setprop_u64(fdt, node, "reg", start); 590 if (ret < 0) 591 goto err; 592 593 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 594 sizeof(fdtsize)); 595 if (ret < 0) 596 goto err; 597 } 598 599 return; 600 err: 601 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 602 panic(); 603 } 604 605 static void bl2_advertise_dram_size(uint32_t product) 606 { 607 uint64_t dram_config[8] = { 608 [0] = 0x400000000ULL, 609 [2] = 0x500000000ULL, 610 [4] = 0x600000000ULL, 611 [6] = 0x700000000ULL, 612 }; 613 614 switch (product) { 615 case PRR_PRODUCT_H3: 616 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 617 /* 4GB(1GBx4) */ 618 dram_config[1] = 0x40000000ULL; 619 dram_config[3] = 0x40000000ULL; 620 dram_config[5] = 0x40000000ULL; 621 dram_config[7] = 0x40000000ULL; 622 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 623 (RCAR_DRAM_CHANNEL == 5) && \ 624 (RCAR_DRAM_SPLIT == 2) 625 /* 4GB(2GBx2 2ch split) */ 626 dram_config[1] = 0x80000000ULL; 627 dram_config[3] = 0x80000000ULL; 628 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 629 /* 8GB(2GBx4: default) */ 630 dram_config[1] = 0x80000000ULL; 631 dram_config[3] = 0x80000000ULL; 632 dram_config[5] = 0x80000000ULL; 633 dram_config[7] = 0x80000000ULL; 634 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 635 break; 636 637 case PRR_PRODUCT_M3: 638 #if (RCAR_GEN3_ULCB == 1) 639 /* 2GB(1GBx2 2ch split) */ 640 dram_config[1] = 0x40000000ULL; 641 dram_config[5] = 0x40000000ULL; 642 #else 643 /* 4GB(2GBx2 2ch split) */ 644 dram_config[1] = 0x80000000ULL; 645 dram_config[5] = 0x80000000ULL; 646 #endif 647 break; 648 649 case PRR_PRODUCT_M3N: 650 /* 2GB(1GBx2) */ 651 dram_config[1] = 0x80000000ULL; 652 break; 653 654 case PRR_PRODUCT_V3M: 655 /* 1GB(512MBx2) */ 656 dram_config[1] = 0x40000000ULL; 657 break; 658 659 case PRR_PRODUCT_E3: 660 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 661 /* 1GB(512MBx2) */ 662 dram_config[1] = 0x40000000ULL; 663 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 664 /* 2GB(512MBx4) */ 665 dram_config[1] = 0x80000000ULL; 666 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 667 /* 4GB(1GBx4) */ 668 dram_config[1] = 0x100000000ULL; 669 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 670 break; 671 672 case PRR_PRODUCT_D3: 673 /* 512MB */ 674 dram_config[1] = 0x20000000ULL; 675 break; 676 } 677 678 bl2_advertise_dram_entries(dram_config); 679 } 680 681 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 682 u_register_t arg3, u_register_t arg4) 683 { 684 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 685 uint32_t product, product_cut, major, minor; 686 int32_t ret; 687 const char *str; 688 const char *unknown = "unknown"; 689 const char *cpu_ca57 = "CA57"; 690 const char *cpu_ca53 = "CA53"; 691 const char *product_m3n = "M3N"; 692 const char *product_h3 = "H3"; 693 const char *product_m3 = "M3"; 694 const char *product_e3 = "E3"; 695 const char *product_d3 = "D3"; 696 const char *product_v3m = "V3M"; 697 const char *lcs_secure = "SE"; 698 const char *lcs_cm = "CM"; 699 const char *lcs_dm = "DM"; 700 const char *lcs_sd = "SD"; 701 const char *lcs_fa = "FA"; 702 const char *sscg_off = "PLL1 nonSSCG Clock select"; 703 const char *sscg_on = "PLL1 SSCG Clock select"; 704 const char *boot_hyper80 = "HyperFlash(80MHz)"; 705 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 706 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 707 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 708 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 709 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 710 const char *boot_hyper160 = "HyperFlash(150MHz)"; 711 #else 712 const char *boot_hyper160 = "HyperFlash(160MHz)"; 713 #endif 714 #if (RCAR_LOSSY_ENABLE == 1) 715 int fcnlnode; 716 #endif 717 718 bl2_init_generic_timer(); 719 720 reg = mmio_read_32(RCAR_MODEMR); 721 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 722 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 723 724 bl2_cpg_init(); 725 726 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 727 boot_cpu == MODEMR_BOOT_CPU_CA53) { 728 rcar_pfc_init(); 729 rcar_console_boot_init(); 730 } 731 732 plat_rcar_gic_driver_init(); 733 plat_rcar_gic_init(); 734 rcar_swdt_init(); 735 736 /* FIQ interrupts are taken to EL3 */ 737 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 738 739 write_daifclr(DAIF_FIQ_BIT); 740 741 reg = read_midr(); 742 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 743 switch (midr) { 744 case MIDR_CA57: 745 str = cpu_ca57; 746 break; 747 case MIDR_CA53: 748 str = cpu_ca53; 749 break; 750 default: 751 str = unknown; 752 break; 753 } 754 755 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 756 version_of_renesas); 757 758 reg = mmio_read_32(RCAR_PRR); 759 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 760 product = reg & PRR_PRODUCT_MASK; 761 762 switch (product) { 763 case PRR_PRODUCT_H3: 764 str = product_h3; 765 break; 766 case PRR_PRODUCT_M3: 767 str = product_m3; 768 break; 769 case PRR_PRODUCT_M3N: 770 str = product_m3n; 771 break; 772 case PRR_PRODUCT_V3M: 773 str = product_v3m; 774 break; 775 case PRR_PRODUCT_E3: 776 str = product_e3; 777 break; 778 case PRR_PRODUCT_D3: 779 str = product_d3; 780 break; 781 default: 782 str = unknown; 783 break; 784 } 785 786 if ((PRR_PRODUCT_M3 == product) && 787 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 788 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 789 /* M3 Ver.1.1 or Ver.1.2 */ 790 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 791 str); 792 } else { 793 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 794 str, 795 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 796 } 797 } else { 798 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 799 major = major + RCAR_MAJOR_OFFSET; 800 minor = reg & RCAR_MINOR_MASK; 801 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 802 } 803 804 if (product == PRR_PRODUCT_E3) { 805 reg = mmio_read_32(RCAR_MODEMR); 806 sscg = reg & RCAR_SSCG_MASK; 807 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 808 NOTICE("BL2: %s\n", str); 809 } 810 811 rcar_get_board_type(&type, &rev); 812 813 switch (type) { 814 case BOARD_SALVATOR_X: 815 case BOARD_KRIEK: 816 case BOARD_STARTER_KIT: 817 case BOARD_SALVATOR_XS: 818 case BOARD_EBISU: 819 case BOARD_STARTER_KIT_PRE: 820 case BOARD_EBISU_4D: 821 case BOARD_DRAAK: 822 case BOARD_EAGLE: 823 break; 824 default: 825 type = BOARD_UNKNOWN; 826 break; 827 } 828 829 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 830 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 831 else { 832 NOTICE("BL2: Board is %s Rev.%d.%d\n", 833 GET_BOARD_NAME(type), 834 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 835 } 836 837 #if RCAR_LSI != RCAR_AUTO 838 if (product != TARGET_PRODUCT) { 839 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 840 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 841 panic(); 842 } 843 #endif 844 rcar_avs_init(); 845 rcar_avs_setting(); 846 847 switch (boot_dev) { 848 case MODEMR_BOOT_DEV_HYPERFLASH160: 849 str = boot_hyper160; 850 break; 851 case MODEMR_BOOT_DEV_HYPERFLASH80: 852 str = boot_hyper80; 853 break; 854 case MODEMR_BOOT_DEV_QSPI_FLASH40: 855 str = boot_qspi40; 856 break; 857 case MODEMR_BOOT_DEV_QSPI_FLASH80: 858 str = boot_qspi80; 859 break; 860 case MODEMR_BOOT_DEV_EMMC_25X1: 861 #if RCAR_LSI == RCAR_D3 862 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 863 panic(); 864 #endif 865 str = boot_emmc25x1; 866 break; 867 case MODEMR_BOOT_DEV_EMMC_50X8: 868 #if RCAR_LSI == RCAR_D3 869 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 870 panic(); 871 #endif 872 str = boot_emmc50x8; 873 break; 874 default: 875 str = unknown; 876 break; 877 } 878 NOTICE("BL2: Boot device is %s\n", str); 879 880 rcar_avs_setting(); 881 reg = rcar_rom_get_lcs(&lcs); 882 if (reg) { 883 str = unknown; 884 goto lcm_state; 885 } 886 887 switch (lcs) { 888 case LCS_CM: 889 str = lcs_cm; 890 break; 891 case LCS_DM: 892 str = lcs_dm; 893 break; 894 case LCS_SD: 895 str = lcs_sd; 896 break; 897 case LCS_SE: 898 str = lcs_secure; 899 break; 900 case LCS_FA: 901 str = lcs_fa; 902 break; 903 default: 904 str = unknown; 905 break; 906 } 907 908 lcm_state: 909 NOTICE("BL2: LCM state is %s\n", str); 910 911 rcar_avs_end(); 912 is_ddr_backup_mode(); 913 914 bl2_tzram_layout.total_base = BL31_BASE; 915 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 916 917 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 918 boot_cpu == MODEMR_BOOT_CPU_CA53) { 919 ret = rcar_dram_init(); 920 if (ret) { 921 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 922 panic(); 923 } 924 rcar_qos_init(); 925 } 926 927 /* Set up FDT */ 928 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 929 if (ret) { 930 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 931 panic(); 932 } 933 934 /* Add platform compatible string */ 935 bl2_populate_compatible_string(fdt); 936 937 /* Print DRAM layout */ 938 bl2_advertise_dram_size(product); 939 940 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 941 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 942 if (rcar_emmc_init() != EMMC_SUCCESS) { 943 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 944 panic(); 945 } 946 rcar_emmc_memcard_power(EMMC_POWER_ON); 947 if (rcar_emmc_mount() != EMMC_SUCCESS) { 948 NOTICE("BL2: Failed to eMMC mount operation.\n"); 949 panic(); 950 } 951 } else { 952 rcar_rpc_init(); 953 rcar_dma_init(); 954 } 955 956 reg = mmio_read_32(RST_WDTRSTCR); 957 reg &= ~WDTRSTCR_RWDT_RSTMSK; 958 reg |= WDTRSTCR_PASSWORD; 959 mmio_write_32(RST_WDTRSTCR, reg); 960 961 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 962 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 963 964 reg = mmio_read_32(RCAR_PRR); 965 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 966 mmio_write_32(CPG_CA57DBGRCR, 967 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 968 969 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 970 mmio_write_32(CPG_CA53DBGRCR, 971 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 972 973 if (product_cut == PRR_PRODUCT_H3_CUT10) { 974 reg = mmio_read_32(CPG_PLL2CR); 975 reg &= ~((uint32_t) 1 << 5); 976 mmio_write_32(CPG_PLL2CR, reg); 977 978 reg = mmio_read_32(CPG_PLL4CR); 979 reg &= ~((uint32_t) 1 << 5); 980 mmio_write_32(CPG_PLL4CR, reg); 981 982 reg = mmio_read_32(CPG_PLL0CR); 983 reg &= ~((uint32_t) 1 << 12); 984 mmio_write_32(CPG_PLL0CR, reg); 985 } 986 #if (RCAR_LOSSY_ENABLE == 1) 987 NOTICE("BL2: Lossy Decomp areas\n"); 988 989 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 990 if (fcnlnode < 0) { 991 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 992 fcnlnode); 993 panic(); 994 } 995 996 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 997 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 998 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 999 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 1000 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 1001 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 1002 #endif 1003 1004 fdt_pack(fdt); 1005 NOTICE("BL2: FDT at %p\n", fdt); 1006 1007 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1008 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1009 rcar_io_emmc_setup(); 1010 else 1011 rcar_io_setup(); 1012 } 1013 1014 void bl2_el3_plat_arch_setup(void) 1015 { 1016 #if RCAR_BL2_DCACHE == 1 1017 NOTICE("BL2: D-Cache enable\n"); 1018 rcar_configure_mmu_el3(BL2_BASE, 1019 BL2_END - BL2_BASE, 1020 BL2_RO_BASE, BL2_RO_LIMIT 1021 #if USE_COHERENT_MEM 1022 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1023 #endif 1024 ); 1025 #endif 1026 } 1027 1028 void bl2_platform_setup(void) 1029 { 1030 1031 } 1032 1033 static void bl2_init_generic_timer(void) 1034 { 1035 /* FIXME: V3M 16.666 MHz ? */ 1036 #if RCAR_LSI == RCAR_D3 1037 uint32_t reg_cntfid = EXTAL_DRAAK; 1038 #elif RCAR_LSI == RCAR_E3 1039 uint32_t reg_cntfid = EXTAL_EBISU; 1040 #else /* RCAR_LSI == RCAR_E3 */ 1041 uint32_t reg; 1042 uint32_t reg_cntfid; 1043 uint32_t modemr; 1044 uint32_t modemr_pll; 1045 uint32_t board_type; 1046 uint32_t board_rev; 1047 uint32_t pll_table[] = { 1048 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1049 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1050 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1051 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1052 }; 1053 1054 modemr = mmio_read_32(RCAR_MODEMR); 1055 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1056 1057 /* Set frequency data in CNTFID0 */ 1058 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1059 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1060 switch (modemr_pll) { 1061 case MD14_MD13_TYPE_0: 1062 rcar_get_board_type(&board_type, &board_rev); 1063 if (BOARD_SALVATOR_XS == board_type) { 1064 reg_cntfid = EXTAL_SALVATOR_XS; 1065 } 1066 break; 1067 case MD14_MD13_TYPE_3: 1068 if (PRR_PRODUCT_H3_CUT10 == reg) { 1069 reg_cntfid = reg_cntfid >> 1U; 1070 } 1071 break; 1072 default: 1073 /* none */ 1074 break; 1075 } 1076 #endif /* RCAR_LSI == RCAR_E3 */ 1077 /* Update memory mapped and register based freqency */ 1078 write_cntfrq_el0((u_register_t )reg_cntfid); 1079 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1080 /* Enable counter */ 1081 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1082 (uint32_t)CNTCR_EN); 1083 } 1084