1 /* 2 * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 #include <stdint.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <bl1/bl1.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <common/desc_image_load.h> 20 #include <common/image_decompress.h> 21 #include <drivers/console.h> 22 #include <drivers/io/io_driver.h> 23 #include <drivers/io/io_storage.h> 24 #include <lib/mmio.h> 25 #include <lib/xlat_tables/xlat_tables_defs.h> 26 #include <plat/common/platform.h> 27 #if RCAR_GEN3_BL33_GZIP == 1 28 #include <tf_gunzip.h> 29 #endif 30 31 #include "avs_driver.h" 32 #include "boot_init_dram.h" 33 #include "cpg_registers.h" 34 #include "board.h" 35 #include "emmc_def.h" 36 #include "emmc_hal.h" 37 #include "emmc_std.h" 38 39 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 40 #include "iic_dvfs.h" 41 #endif 42 43 #include "io_common.h" 44 #include "io_rcar.h" 45 #include "qos_init.h" 46 #include "rcar_def.h" 47 #include "rcar_private.h" 48 #include "rcar_version.h" 49 #include "rom_api.h" 50 51 #if RCAR_BL2_DCACHE == 1 52 /* 53 * Following symbols are only used during plat_arch_setup() only 54 * when RCAR_BL2_DCACHE is enabled. 55 */ 56 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 57 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 58 59 #if USE_COHERENT_MEM 60 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 61 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 62 #endif 63 64 #endif 65 66 extern void plat_rcar_gic_driver_init(void); 67 extern void plat_rcar_gic_init(void); 68 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 69 extern void bl2_system_cpg_init(void); 70 extern void bl2_secure_setting(void); 71 extern void bl2_cpg_init(void); 72 extern void rcar_io_emmc_setup(void); 73 extern void rcar_io_setup(void); 74 extern void rcar_swdt_release(void); 75 extern void rcar_swdt_init(void); 76 extern void rcar_rpc_init(void); 77 extern void rcar_pfc_init(void); 78 extern void rcar_dma_init(void); 79 80 static void bl2_init_generic_timer(void); 81 82 /* R-Car Gen3 product check */ 83 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 84 #define TARGET_PRODUCT PRR_PRODUCT_H3 85 #define TARGET_NAME "R-Car H3" 86 #elif RCAR_LSI == RCAR_M3 87 #define TARGET_PRODUCT PRR_PRODUCT_M3 88 #define TARGET_NAME "R-Car M3" 89 #elif RCAR_LSI == RCAR_M3N 90 #define TARGET_PRODUCT PRR_PRODUCT_M3N 91 #define TARGET_NAME "R-Car M3N" 92 #elif RCAR_LSI == RCAR_V3M 93 #define TARGET_PRODUCT PRR_PRODUCT_V3M 94 #define TARGET_NAME "R-Car V3M" 95 #elif RCAR_LSI == RCAR_E3 96 #define TARGET_PRODUCT PRR_PRODUCT_E3 97 #define TARGET_NAME "R-Car E3" 98 #elif RCAR_LSI == RCAR_D3 99 #define TARGET_PRODUCT PRR_PRODUCT_D3 100 #define TARGET_NAME "R-Car D3" 101 #elif RCAR_LSI == RCAR_AUTO 102 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 103 #endif 104 105 #if (RCAR_LSI == RCAR_E3) 106 #define GPIO_INDT (GPIO_INDT6) 107 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 108 #else 109 #define GPIO_INDT (GPIO_INDT1) 110 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 111 #endif 112 113 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 114 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 115 assert_bl31_params_do_not_fit_in_shared_memory); 116 117 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 118 119 /* FDT with DRAM configuration */ 120 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 121 static void *fdt = (void *)fdt_blob; 122 123 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 124 char *string) 125 { 126 /* Just need enough space to store 64 bit decimal integer */ 127 char num_buf[20]; 128 int i = 0; 129 unsigned int rem; 130 131 do { 132 rem = unum % radix; 133 if (rem < 0xa) 134 num_buf[i] = '0' + rem; 135 else 136 num_buf[i] = 'a' + (rem - 0xa); 137 i++; 138 unum /= radix; 139 } while (unum > 0U); 140 141 while (--i >= 0) 142 *string++ = num_buf[i]; 143 *string = 0; 144 } 145 146 #if (RCAR_LOSSY_ENABLE == 1) 147 typedef struct bl2_lossy_info { 148 uint32_t magic; 149 uint32_t a0; 150 uint32_t b0; 151 } bl2_lossy_info_t; 152 153 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 154 uint64_t end_addr, uint32_t format, 155 uint32_t enable, int fcnlnode) 156 { 157 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 158 char nodename[40] = { 0 }; 159 int ret, node; 160 161 /* Ignore undefined addresses */ 162 if (start_addr == 0 && end_addr == 0) 163 return; 164 165 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 166 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 167 168 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 169 if (ret < 0) { 170 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 171 panic(); 172 } 173 174 ret = fdt_setprop_string(fdt, node, "compatible", 175 "renesas,lossy-decompression"); 176 if (ret < 0) { 177 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 178 panic(); 179 } 180 181 ret = fdt_appendprop_string(fdt, node, "compatible", 182 "shared-dma-pool"); 183 if (ret < 0) { 184 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 185 panic(); 186 } 187 188 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 189 if (ret < 0) { 190 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 191 panic(); 192 } 193 194 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 195 if (ret < 0) { 196 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 197 panic(); 198 } 199 200 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 201 if (ret < 0) { 202 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 203 panic(); 204 } 205 206 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 207 if (ret < 0) { 208 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 209 panic(); 210 } 211 } 212 213 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 214 uint64_t end_addr, uint32_t format, 215 uint32_t enable, int fcnlnode) 216 { 217 bl2_lossy_info_t info; 218 uint32_t reg; 219 220 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 221 222 reg = format | (start_addr >> 20); 223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 224 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 225 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 226 227 info.magic = 0x12345678U; 228 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 229 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 230 231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 232 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 233 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 234 235 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 236 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 237 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 238 } 239 240 static int bl2_create_reserved_memory(void) 241 { 242 int ret; 243 244 int fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 245 if (fcnlnode < 0) { 246 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 247 fcnlnode); 248 panic(); 249 } 250 251 ret = fdt_setprop(fdt, fcnlnode, "ranges", NULL, 0); 252 if (ret < 0) { 253 NOTICE("BL2: Cannot add FCNL ranges prop (ret=%i)\n", ret); 254 panic(); 255 } 256 257 ret = fdt_setprop_u32(fdt, fcnlnode, "#address-cells", 2); 258 if (ret < 0) { 259 NOTICE("BL2: Cannot add FCNL #address-cells prop (ret=%i)\n", ret); 260 panic(); 261 } 262 263 ret = fdt_setprop_u32(fdt, fcnlnode, "#size-cells", 2); 264 if (ret < 0) { 265 NOTICE("BL2: Cannot add FCNL #size-cells prop (ret=%i)\n", ret); 266 panic(); 267 } 268 269 return fcnlnode; 270 } 271 272 static void bl2_create_fcnl_reserved_memory(void) 273 { 274 int fcnlnode; 275 276 NOTICE("BL2: Lossy Decomp areas\n"); 277 278 fcnlnode = bl2_create_reserved_memory(); 279 280 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 281 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 282 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 283 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 284 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 285 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 286 } 287 #else 288 static void bl2_create_fcnl_reserved_memory(void) {} 289 #endif 290 291 void bl2_plat_flush_bl31_params(void) 292 { 293 uint32_t product_cut, product, cut; 294 uint32_t boot_dev, boot_cpu; 295 uint32_t lcs, reg, val; 296 297 reg = mmio_read_32(RCAR_MODEMR); 298 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 299 300 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 301 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 302 emmc_terminate(); 303 304 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 305 bl2_secure_setting(); 306 307 reg = mmio_read_32(RCAR_PRR); 308 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 309 product = reg & PRR_PRODUCT_MASK; 310 cut = reg & PRR_CUT_MASK; 311 312 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 313 goto tlb; 314 315 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 316 goto tlb; 317 318 /* Disable MFIS write protection */ 319 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 320 321 tlb: 322 reg = mmio_read_32(RCAR_MODEMR); 323 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 324 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 325 boot_cpu != MODEMR_BOOT_CPU_CA53) 326 goto mmu; 327 328 if (product_cut == PRR_PRODUCT_H3_CUT20) { 329 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 330 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 331 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 332 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 333 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 334 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 335 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 336 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 337 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 338 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 339 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 340 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 341 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 342 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 343 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 344 } 345 346 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 347 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 348 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 349 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 350 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 351 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 352 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 353 354 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 355 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 356 } 357 358 mmu: 359 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 360 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 361 362 val = rcar_rom_get_lcs(&lcs); 363 if (val) { 364 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 365 panic(); 366 } 367 368 if (lcs == LCS_SE) 369 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 370 371 rcar_swdt_release(); 372 bl2_system_cpg_init(); 373 374 #if RCAR_BL2_DCACHE == 1 375 /* Disable data cache (clean and invalidate) */ 376 disable_mmu_el3(); 377 #endif 378 } 379 380 static uint32_t is_ddr_backup_mode(void) 381 { 382 #if RCAR_SYSTEM_SUSPEND 383 static uint32_t reason = RCAR_COLD_BOOT; 384 static uint32_t once; 385 386 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 387 uint8_t data; 388 #endif 389 if (once) 390 return reason; 391 392 once = 1; 393 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 394 return reason; 395 396 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 397 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 398 ERROR("BL2: REG Keep10 READ ERROR.\n"); 399 panic(); 400 } 401 402 if (KEEP10_MAGIC != data) 403 reason = RCAR_WARM_BOOT; 404 #else 405 reason = RCAR_WARM_BOOT; 406 #endif 407 return reason; 408 #else 409 return RCAR_COLD_BOOT; 410 #endif 411 } 412 413 #if RCAR_GEN3_BL33_GZIP == 1 414 void bl2_plat_preload_setup(void) 415 { 416 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip); 417 } 418 #endif 419 420 int bl2_plat_handle_pre_image_load(unsigned int image_id) 421 { 422 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 423 bl_mem_params_node_t *bl_mem_params; 424 425 bl_mem_params = get_bl_mem_params_node(image_id); 426 427 #if RCAR_GEN3_BL33_GZIP == 1 428 if (image_id == BL33_IMAGE_ID) { 429 image_decompress_prepare(&bl_mem_params->image_info); 430 } 431 #endif 432 433 if (image_id != BL31_IMAGE_ID) 434 return 0; 435 436 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 437 goto cold_boot; 438 439 *boot_kind = RCAR_WARM_BOOT; 440 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 441 442 console_flush(); 443 bl2_plat_flush_bl31_params(); 444 445 /* will not return */ 446 bl2_enter_bl31(&bl_mem_params->ep_info); 447 448 cold_boot: 449 *boot_kind = RCAR_COLD_BOOT; 450 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 451 452 return 0; 453 } 454 455 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 456 { 457 uint32_t cert, len; 458 int ret; 459 460 ret = rcar_get_certificate(certid, &cert); 461 if (ret) { 462 ERROR("%s : cert file load error", __func__); 463 return 1; 464 } 465 466 rcar_read_certificate((uint64_t) cert, &len, dest); 467 468 return 0; 469 } 470 471 int bl2_plat_handle_post_image_load(unsigned int image_id) 472 { 473 static bl2_to_bl31_params_mem_t *params; 474 bl_mem_params_node_t *bl_mem_params; 475 uintptr_t dest; 476 int ret; 477 478 if (!params) { 479 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 480 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 481 } 482 483 bl_mem_params = get_bl_mem_params_node(image_id); 484 485 switch (image_id) { 486 case BL31_IMAGE_ID: 487 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 488 &dest); 489 if (!ret) 490 bl_mem_params->image_info.image_base = dest; 491 break; 492 case BL32_IMAGE_ID: 493 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 494 &dest); 495 if (!ret) 496 bl_mem_params->image_info.image_base = dest; 497 498 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 499 sizeof(entry_point_info_t)); 500 break; 501 case BL33_IMAGE_ID: 502 #if RCAR_GEN3_BL33_GZIP == 1 503 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) { 504 /* decompress gzip-compressed image */ 505 ret = image_decompress(&bl_mem_params->image_info); 506 if (ret != 0) { 507 return ret; 508 } 509 } else { 510 /* plain image, copy it in place */ 511 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE, 512 bl_mem_params->image_info.image_size); 513 } 514 #endif 515 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 516 sizeof(entry_point_info_t)); 517 break; 518 } 519 520 return 0; 521 } 522 523 struct meminfo *bl2_plat_sec_mem_layout(void) 524 { 525 return &bl2_tzram_layout; 526 } 527 528 static void bl2_populate_compatible_string(void *dt) 529 { 530 uint32_t board_type; 531 uint32_t board_rev; 532 uint32_t reg; 533 int ret; 534 535 fdt_setprop_u32(dt, 0, "#address-cells", 2); 536 fdt_setprop_u32(dt, 0, "#size-cells", 2); 537 538 /* Populate compatible string */ 539 rcar_get_board_type(&board_type, &board_rev); 540 switch (board_type) { 541 case BOARD_SALVATOR_X: 542 ret = fdt_setprop_string(dt, 0, "compatible", 543 "renesas,salvator-x"); 544 break; 545 case BOARD_SALVATOR_XS: 546 ret = fdt_setprop_string(dt, 0, "compatible", 547 "renesas,salvator-xs"); 548 break; 549 case BOARD_STARTER_KIT: 550 ret = fdt_setprop_string(dt, 0, "compatible", 551 "renesas,m3ulcb"); 552 break; 553 case BOARD_STARTER_KIT_PRE: 554 ret = fdt_setprop_string(dt, 0, "compatible", 555 "renesas,h3ulcb"); 556 break; 557 case BOARD_EAGLE: 558 ret = fdt_setprop_string(dt, 0, "compatible", 559 "renesas,eagle"); 560 break; 561 case BOARD_EBISU: 562 case BOARD_EBISU_4D: 563 ret = fdt_setprop_string(dt, 0, "compatible", 564 "renesas,ebisu"); 565 break; 566 case BOARD_DRAAK: 567 ret = fdt_setprop_string(dt, 0, "compatible", 568 "renesas,draak"); 569 break; 570 default: 571 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 572 panic(); 573 } 574 575 if (ret < 0) { 576 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 577 panic(); 578 } 579 580 reg = mmio_read_32(RCAR_PRR); 581 switch (reg & PRR_PRODUCT_MASK) { 582 case PRR_PRODUCT_H3: 583 ret = fdt_appendprop_string(dt, 0, "compatible", 584 "renesas,r8a7795"); 585 break; 586 case PRR_PRODUCT_M3: 587 ret = fdt_appendprop_string(dt, 0, "compatible", 588 "renesas,r8a7796"); 589 break; 590 case PRR_PRODUCT_M3N: 591 ret = fdt_appendprop_string(dt, 0, "compatible", 592 "renesas,r8a77965"); 593 break; 594 case PRR_PRODUCT_V3M: 595 ret = fdt_appendprop_string(dt, 0, "compatible", 596 "renesas,r8a77970"); 597 break; 598 case PRR_PRODUCT_E3: 599 ret = fdt_appendprop_string(dt, 0, "compatible", 600 "renesas,r8a77990"); 601 break; 602 case PRR_PRODUCT_D3: 603 ret = fdt_appendprop_string(dt, 0, "compatible", 604 "renesas,r8a77995"); 605 break; 606 default: 607 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 608 panic(); 609 } 610 611 if (ret < 0) { 612 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 613 panic(); 614 } 615 } 616 617 static void bl2_add_rpc_node(void) 618 { 619 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0) 620 int ret, node; 621 622 node = ret = fdt_add_subnode(fdt, 0, "soc"); 623 if (ret < 0) { 624 goto err; 625 } 626 627 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000"); 628 if (ret < 0) { 629 goto err; 630 } 631 632 ret = fdt_setprop_string(fdt, node, "status", "okay"); 633 if (ret < 0) { 634 goto err; 635 } 636 637 return; 638 err: 639 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret); 640 panic(); 641 #endif 642 } 643 644 static void bl2_add_dram_entry(uint64_t start, uint64_t size) 645 { 646 char nodename[32] = { 0 }; 647 uint64_t fdtsize; 648 int ret, node; 649 650 fdtsize = cpu_to_fdt64(size); 651 652 snprintf(nodename, sizeof(nodename), "memory@"); 653 unsigned_num_print(start, 16, nodename + strlen(nodename)); 654 node = ret = fdt_add_subnode(fdt, 0, nodename); 655 if (ret < 0) { 656 goto err; 657 } 658 659 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 660 if (ret < 0) { 661 goto err; 662 } 663 664 ret = fdt_setprop_u64(fdt, node, "reg", start); 665 if (ret < 0) { 666 goto err; 667 } 668 669 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 670 sizeof(fdtsize)); 671 if (ret < 0) { 672 goto err; 673 } 674 675 return; 676 err: 677 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n", 678 start, start + size - 1, ret); 679 panic(); 680 } 681 682 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 683 { 684 uint64_t start, size, size32; 685 int chan; 686 687 for (chan = 0; chan < 4; chan++) { 688 start = dram_config[2 * chan]; 689 size = dram_config[2 * chan + 1]; 690 if (!size) 691 continue; 692 693 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n", 694 chan, start, start + size - 1, 695 (size >> 30) ? : size >> 20, 696 (size >> 30) ? "G" : "M"); 697 } 698 699 /* 700 * We add the DT nodes in reverse order here. The fdt_add_subnode() 701 * adds the DT node before the first existing DT node, so we have 702 * to add them in reverse order to get nodes sorted by address in 703 * the resulting DT. 704 */ 705 for (chan = 3; chan >= 0; chan--) { 706 start = dram_config[2 * chan]; 707 size = dram_config[2 * chan + 1]; 708 if (!size) 709 continue; 710 711 /* 712 * Channel 0 is mapped in 32bit space and the first 713 * 128 MiB are reserved and the maximum size is 2GiB. 714 */ 715 if (chan == 0) { 716 /* Limit the 32bit entry to 2 GiB - 128 MiB */ 717 size32 = size - 0x8000000U; 718 if (size32 >= 0x78000000U) { 719 size32 = 0x78000000U; 720 } 721 722 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */ 723 bl2_add_dram_entry(0x48000000, size32); 724 725 /* 726 * If channel 0 is less than 2 GiB long, the 727 * entire memory fits into the 32bit space entry, 728 * so move on to the next channel. 729 */ 730 if (size <= 0x80000000U) { 731 continue; 732 } 733 734 /* 735 * If channel 0 is more than 2 GiB long, emit 736 * another entry which covers the rest of the 737 * memory in channel 0, in the 64bit space. 738 * 739 * Start of this new entry is at 2 GiB offset 740 * from the beginning of the 64bit channel 0 741 * address, size is 2 GiB shorter than total 742 * size of the channel. 743 */ 744 start += 0x80000000U; 745 size -= 0x80000000U; 746 } 747 748 bl2_add_dram_entry(start, size); 749 } 750 } 751 752 static void bl2_advertise_dram_size(uint32_t product) 753 { 754 uint64_t dram_config[8] = { 755 [0] = 0x400000000ULL, 756 [2] = 0x500000000ULL, 757 [4] = 0x600000000ULL, 758 [6] = 0x700000000ULL, 759 }; 760 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; 761 762 switch (product) { 763 case PRR_PRODUCT_H3: 764 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 765 /* 4GB(1GBx4) */ 766 dram_config[1] = 0x40000000ULL; 767 dram_config[3] = 0x40000000ULL; 768 dram_config[5] = 0x40000000ULL; 769 dram_config[7] = 0x40000000ULL; 770 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 771 (RCAR_DRAM_CHANNEL == 5) && \ 772 (RCAR_DRAM_SPLIT == 2) 773 /* 4GB(2GBx2 2ch split) */ 774 dram_config[1] = 0x80000000ULL; 775 dram_config[3] = 0x80000000ULL; 776 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 777 /* 8GB(2GBx4: default) */ 778 dram_config[1] = 0x80000000ULL; 779 dram_config[3] = 0x80000000ULL; 780 dram_config[5] = 0x80000000ULL; 781 dram_config[7] = 0x80000000ULL; 782 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 783 break; 784 785 case PRR_PRODUCT_M3: 786 if (cut < PRR_PRODUCT_30) { 787 #if (RCAR_GEN3_ULCB == 1) 788 /* 2GB(1GBx2 2ch split) */ 789 dram_config[1] = 0x40000000ULL; 790 dram_config[5] = 0x40000000ULL; 791 #else 792 /* 4GB(2GBx2 2ch split) */ 793 dram_config[1] = 0x80000000ULL; 794 dram_config[5] = 0x80000000ULL; 795 #endif 796 } else { 797 /* 8GB(2GBx4 2ch split) */ 798 dram_config[1] = 0x100000000ULL; 799 dram_config[5] = 0x100000000ULL; 800 } 801 break; 802 803 case PRR_PRODUCT_M3N: 804 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2) 805 /* 4GB(4GBx1) */ 806 dram_config[1] = 0x100000000ULL; 807 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) 808 /* 2GB(1GBx2) */ 809 dram_config[1] = 0x80000000ULL; 810 #endif 811 break; 812 813 case PRR_PRODUCT_V3M: 814 /* 1GB(512MBx2) */ 815 dram_config[1] = 0x40000000ULL; 816 break; 817 818 case PRR_PRODUCT_E3: 819 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 820 /* 1GB(512MBx2) */ 821 dram_config[1] = 0x40000000ULL; 822 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 823 /* 2GB(512MBx4) */ 824 dram_config[1] = 0x80000000ULL; 825 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 826 /* 4GB(1GBx4) */ 827 dram_config[1] = 0x100000000ULL; 828 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 829 break; 830 831 case PRR_PRODUCT_D3: 832 /* 512MB */ 833 dram_config[1] = 0x20000000ULL; 834 break; 835 } 836 837 bl2_advertise_dram_entries(dram_config); 838 } 839 840 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 841 u_register_t arg3, u_register_t arg4) 842 { 843 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 844 uint32_t product, product_cut, major, minor; 845 int32_t ret; 846 const char *str; 847 const char *unknown = "unknown"; 848 const char *cpu_ca57 = "CA57"; 849 const char *cpu_ca53 = "CA53"; 850 const char *product_m3n = "M3N"; 851 const char *product_h3 = "H3"; 852 const char *product_m3 = "M3"; 853 const char *product_e3 = "E3"; 854 const char *product_d3 = "D3"; 855 const char *product_v3m = "V3M"; 856 const char *lcs_secure = "SE"; 857 const char *lcs_cm = "CM"; 858 const char *lcs_dm = "DM"; 859 const char *lcs_sd = "SD"; 860 const char *lcs_fa = "FA"; 861 const char *sscg_off = "PLL1 nonSSCG Clock select"; 862 const char *sscg_on = "PLL1 SSCG Clock select"; 863 const char *boot_hyper80 = "HyperFlash(80MHz)"; 864 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 865 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 866 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 867 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 868 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 869 const char *boot_hyper160 = "HyperFlash(150MHz)"; 870 #else 871 const char *boot_hyper160 = "HyperFlash(160MHz)"; 872 #endif 873 874 bl2_init_generic_timer(); 875 876 reg = mmio_read_32(RCAR_MODEMR); 877 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 878 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 879 880 bl2_cpg_init(); 881 882 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 883 boot_cpu == MODEMR_BOOT_CPU_CA53) { 884 rcar_pfc_init(); 885 rcar_console_boot_init(); 886 } 887 888 plat_rcar_gic_driver_init(); 889 plat_rcar_gic_init(); 890 rcar_swdt_init(); 891 892 /* FIQ interrupts are taken to EL3 */ 893 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 894 895 write_daifclr(DAIF_FIQ_BIT); 896 897 reg = read_midr(); 898 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 899 switch (midr) { 900 case MIDR_CA57: 901 str = cpu_ca57; 902 break; 903 case MIDR_CA53: 904 str = cpu_ca53; 905 break; 906 default: 907 str = unknown; 908 break; 909 } 910 911 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 912 version_of_renesas); 913 914 reg = mmio_read_32(RCAR_PRR); 915 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 916 product = reg & PRR_PRODUCT_MASK; 917 918 switch (product) { 919 case PRR_PRODUCT_H3: 920 str = product_h3; 921 break; 922 case PRR_PRODUCT_M3: 923 str = product_m3; 924 break; 925 case PRR_PRODUCT_M3N: 926 str = product_m3n; 927 break; 928 case PRR_PRODUCT_V3M: 929 str = product_v3m; 930 break; 931 case PRR_PRODUCT_E3: 932 str = product_e3; 933 break; 934 case PRR_PRODUCT_D3: 935 str = product_d3; 936 break; 937 default: 938 str = unknown; 939 break; 940 } 941 942 if ((PRR_PRODUCT_M3 == product) && 943 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 944 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 945 /* M3 Ver.1.1 or Ver.1.2 */ 946 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 947 str); 948 } else { 949 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 950 str, 951 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 952 } 953 } else if (product == PRR_PRODUCT_D3) { 954 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) { 955 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str); 956 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 957 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str); 958 } else { 959 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str); 960 } 961 } else { 962 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 963 major = major + RCAR_MAJOR_OFFSET; 964 minor = reg & RCAR_MINOR_MASK; 965 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 966 } 967 968 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) { 969 reg = mmio_read_32(RCAR_MODEMR); 970 sscg = reg & RCAR_SSCG_MASK; 971 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 972 NOTICE("BL2: %s\n", str); 973 } 974 975 rcar_get_board_type(&type, &rev); 976 977 switch (type) { 978 case BOARD_SALVATOR_X: 979 case BOARD_KRIEK: 980 case BOARD_STARTER_KIT: 981 case BOARD_SALVATOR_XS: 982 case BOARD_EBISU: 983 case BOARD_STARTER_KIT_PRE: 984 case BOARD_EBISU_4D: 985 case BOARD_DRAAK: 986 case BOARD_EAGLE: 987 break; 988 default: 989 type = BOARD_UNKNOWN; 990 break; 991 } 992 993 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 994 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 995 else { 996 NOTICE("BL2: Board is %s Rev.%d.%d\n", 997 GET_BOARD_NAME(type), 998 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 999 } 1000 1001 #if RCAR_LSI != RCAR_AUTO 1002 if (product != TARGET_PRODUCT) { 1003 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 1004 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 1005 panic(); 1006 } 1007 #endif 1008 rcar_avs_init(); 1009 rcar_avs_setting(); 1010 1011 switch (boot_dev) { 1012 case MODEMR_BOOT_DEV_HYPERFLASH160: 1013 str = boot_hyper160; 1014 break; 1015 case MODEMR_BOOT_DEV_HYPERFLASH80: 1016 str = boot_hyper80; 1017 break; 1018 case MODEMR_BOOT_DEV_QSPI_FLASH40: 1019 str = boot_qspi40; 1020 break; 1021 case MODEMR_BOOT_DEV_QSPI_FLASH80: 1022 str = boot_qspi80; 1023 break; 1024 case MODEMR_BOOT_DEV_EMMC_25X1: 1025 #if RCAR_LSI == RCAR_D3 1026 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 1027 panic(); 1028 #endif 1029 str = boot_emmc25x1; 1030 break; 1031 case MODEMR_BOOT_DEV_EMMC_50X8: 1032 str = boot_emmc50x8; 1033 break; 1034 default: 1035 str = unknown; 1036 break; 1037 } 1038 NOTICE("BL2: Boot device is %s\n", str); 1039 1040 rcar_avs_setting(); 1041 reg = rcar_rom_get_lcs(&lcs); 1042 if (reg) { 1043 str = unknown; 1044 goto lcm_state; 1045 } 1046 1047 switch (lcs) { 1048 case LCS_CM: 1049 str = lcs_cm; 1050 break; 1051 case LCS_DM: 1052 str = lcs_dm; 1053 break; 1054 case LCS_SD: 1055 str = lcs_sd; 1056 break; 1057 case LCS_SE: 1058 str = lcs_secure; 1059 break; 1060 case LCS_FA: 1061 str = lcs_fa; 1062 break; 1063 default: 1064 str = unknown; 1065 break; 1066 } 1067 1068 lcm_state: 1069 NOTICE("BL2: LCM state is %s\n", str); 1070 1071 rcar_avs_end(); 1072 is_ddr_backup_mode(); 1073 1074 bl2_tzram_layout.total_base = BL31_BASE; 1075 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 1076 1077 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 1078 boot_cpu == MODEMR_BOOT_CPU_CA53) { 1079 ret = rcar_dram_init(); 1080 if (ret) { 1081 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 1082 panic(); 1083 } 1084 rcar_qos_init(); 1085 } 1086 1087 /* Set up FDT */ 1088 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 1089 if (ret) { 1090 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 1091 panic(); 1092 } 1093 1094 /* Add platform compatible string */ 1095 bl2_populate_compatible_string(fdt); 1096 1097 /* Enable RPC if unlocked */ 1098 bl2_add_rpc_node(); 1099 1100 /* Print DRAM layout */ 1101 bl2_advertise_dram_size(product); 1102 1103 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1104 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 1105 if (rcar_emmc_init() != EMMC_SUCCESS) { 1106 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 1107 panic(); 1108 } 1109 rcar_emmc_memcard_power(EMMC_POWER_ON); 1110 if (rcar_emmc_mount() != EMMC_SUCCESS) { 1111 NOTICE("BL2: Failed to eMMC mount operation.\n"); 1112 panic(); 1113 } 1114 } else { 1115 rcar_rpc_init(); 1116 rcar_dma_init(); 1117 } 1118 1119 reg = mmio_read_32(RST_WDTRSTCR); 1120 reg &= ~WDTRSTCR_RWDT_RSTMSK; 1121 reg |= WDTRSTCR_PASSWORD; 1122 mmio_write_32(RST_WDTRSTCR, reg); 1123 1124 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 1125 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 1126 1127 reg = mmio_read_32(RCAR_PRR); 1128 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 1129 mmio_write_32(CPG_CA57DBGRCR, 1130 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 1131 1132 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 1133 mmio_write_32(CPG_CA53DBGRCR, 1134 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 1135 1136 if (product_cut == PRR_PRODUCT_H3_CUT10) { 1137 reg = mmio_read_32(CPG_PLL2CR); 1138 reg &= ~((uint32_t) 1 << 5); 1139 mmio_write_32(CPG_PLL2CR, reg); 1140 1141 reg = mmio_read_32(CPG_PLL4CR); 1142 reg &= ~((uint32_t) 1 << 5); 1143 mmio_write_32(CPG_PLL4CR, reg); 1144 1145 reg = mmio_read_32(CPG_PLL0CR); 1146 reg &= ~((uint32_t) 1 << 12); 1147 mmio_write_32(CPG_PLL0CR, reg); 1148 } 1149 1150 bl2_create_fcnl_reserved_memory(); 1151 1152 fdt_pack(fdt); 1153 NOTICE("BL2: FDT at %p\n", fdt); 1154 1155 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1156 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1157 rcar_io_emmc_setup(); 1158 else 1159 rcar_io_setup(); 1160 } 1161 1162 void bl2_el3_plat_arch_setup(void) 1163 { 1164 #if RCAR_BL2_DCACHE == 1 1165 NOTICE("BL2: D-Cache enable\n"); 1166 rcar_configure_mmu_el3(BL2_BASE, 1167 BL2_END - BL2_BASE, 1168 BL2_RO_BASE, BL2_RO_LIMIT 1169 #if USE_COHERENT_MEM 1170 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1171 #endif 1172 ); 1173 #endif 1174 } 1175 1176 void bl2_platform_setup(void) 1177 { 1178 1179 } 1180 1181 static void bl2_init_generic_timer(void) 1182 { 1183 /* FIXME: V3M 16.666 MHz ? */ 1184 #if RCAR_LSI == RCAR_D3 1185 uint32_t reg_cntfid = EXTAL_DRAAK; 1186 #elif RCAR_LSI == RCAR_E3 1187 uint32_t reg_cntfid = EXTAL_EBISU; 1188 #else /* RCAR_LSI == RCAR_E3 */ 1189 uint32_t reg; 1190 uint32_t reg_cntfid; 1191 uint32_t modemr; 1192 uint32_t modemr_pll; 1193 uint32_t board_type; 1194 uint32_t board_rev; 1195 uint32_t pll_table[] = { 1196 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1197 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1198 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1199 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1200 }; 1201 1202 modemr = mmio_read_32(RCAR_MODEMR); 1203 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1204 1205 /* Set frequency data in CNTFID0 */ 1206 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1207 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1208 switch (modemr_pll) { 1209 case MD14_MD13_TYPE_0: 1210 rcar_get_board_type(&board_type, &board_rev); 1211 if (BOARD_SALVATOR_XS == board_type) { 1212 reg_cntfid = EXTAL_SALVATOR_XS; 1213 } 1214 break; 1215 case MD14_MD13_TYPE_3: 1216 if (PRR_PRODUCT_H3_CUT10 == reg) { 1217 reg_cntfid = reg_cntfid >> 1U; 1218 } 1219 break; 1220 default: 1221 /* none */ 1222 break; 1223 } 1224 #endif /* RCAR_LSI == RCAR_E3 */ 1225 /* Update memory mapped and register based frequency */ 1226 write_cntfrq_el0((u_register_t )reg_cntfid); 1227 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1228 /* Enable counter */ 1229 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1230 (uint32_t)CNTCR_EN); 1231 } 1232