1 /* 2 * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 #if RCAR_BL2_DCACHE == 1 43 /* 44 * Following symbols are only used during plat_arch_setup() only 45 * when RCAR_BL2_DCACHE is enabled. 46 */ 47 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 48 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 49 50 #if USE_COHERENT_MEM 51 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 52 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 53 #endif 54 55 #endif 56 57 extern void plat_rcar_gic_driver_init(void); 58 extern void plat_rcar_gic_init(void); 59 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 60 extern void bl2_system_cpg_init(void); 61 extern void bl2_secure_setting(void); 62 extern void bl2_cpg_init(void); 63 extern void rcar_io_emmc_setup(void); 64 extern void rcar_io_setup(void); 65 extern void rcar_swdt_release(void); 66 extern void rcar_swdt_init(void); 67 extern void rcar_rpc_init(void); 68 extern void rcar_pfc_init(void); 69 extern void rcar_dma_init(void); 70 71 static void bl2_init_generic_timer(void); 72 73 /* R-Car Gen3 product check */ 74 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 75 #define TARGET_PRODUCT PRR_PRODUCT_H3 76 #define TARGET_NAME "R-Car H3" 77 #elif RCAR_LSI == RCAR_M3 78 #define TARGET_PRODUCT PRR_PRODUCT_M3 79 #define TARGET_NAME "R-Car M3" 80 #elif RCAR_LSI == RCAR_M3N 81 #define TARGET_PRODUCT PRR_PRODUCT_M3N 82 #define TARGET_NAME "R-Car M3N" 83 #elif RCAR_LSI == RCAR_V3M 84 #define TARGET_PRODUCT PRR_PRODUCT_V3M 85 #define TARGET_NAME "R-Car V3M" 86 #elif RCAR_LSI == RCAR_E3 87 #define TARGET_PRODUCT PRR_PRODUCT_E3 88 #define TARGET_NAME "R-Car E3" 89 #elif RCAR_LSI == RCAR_D3 90 #define TARGET_PRODUCT PRR_PRODUCT_D3 91 #define TARGET_NAME "R-Car D3" 92 #elif RCAR_LSI == RCAR_AUTO 93 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 94 #endif 95 96 #if (RCAR_LSI == RCAR_E3) 97 #define GPIO_INDT (GPIO_INDT6) 98 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 99 #else 100 #define GPIO_INDT (GPIO_INDT1) 101 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 102 #endif 103 104 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 105 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 106 assert_bl31_params_do_not_fit_in_shared_memory); 107 108 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 109 110 /* FDT with DRAM configuration */ 111 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 112 static void *fdt = (void *)fdt_blob; 113 114 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 115 char *string) 116 { 117 /* Just need enough space to store 64 bit decimal integer */ 118 char num_buf[20]; 119 int i = 0; 120 unsigned int rem; 121 122 do { 123 rem = unum % radix; 124 if (rem < 0xa) 125 num_buf[i] = '0' + rem; 126 else 127 num_buf[i] = 'a' + (rem - 0xa); 128 i++; 129 unum /= radix; 130 } while (unum > 0U); 131 132 while (--i >= 0) 133 *string++ = num_buf[i]; 134 } 135 136 #if (RCAR_LOSSY_ENABLE == 1) 137 typedef struct bl2_lossy_info { 138 uint32_t magic; 139 uint32_t a0; 140 uint32_t b0; 141 } bl2_lossy_info_t; 142 143 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 144 uint64_t end_addr, uint32_t format, 145 uint32_t enable, int fcnlnode) 146 { 147 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 148 char nodename[40] = { 0 }; 149 int ret, node; 150 151 /* Ignore undefined addresses */ 152 if (start_addr == 0 && end_addr == 0) 153 return; 154 155 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 156 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 157 158 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 159 if (ret < 0) { 160 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 161 panic(); 162 } 163 164 ret = fdt_setprop_string(fdt, node, "compatible", 165 "renesas,lossy-decompression"); 166 if (ret < 0) { 167 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 168 panic(); 169 } 170 171 ret = fdt_appendprop_string(fdt, node, "compatible", 172 "shared-dma-pool"); 173 if (ret < 0) { 174 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 175 panic(); 176 } 177 178 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 179 if (ret < 0) { 180 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 181 panic(); 182 } 183 184 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 185 if (ret < 0) { 186 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 187 panic(); 188 } 189 190 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 191 if (ret < 0) { 192 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 193 panic(); 194 } 195 196 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 197 if (ret < 0) { 198 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 199 panic(); 200 } 201 } 202 203 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 204 uint64_t end_addr, uint32_t format, 205 uint32_t enable, int fcnlnode) 206 { 207 bl2_lossy_info_t info; 208 uint32_t reg; 209 210 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 211 212 reg = format | (start_addr >> 20); 213 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 214 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 215 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 216 217 info.magic = 0x12345678U; 218 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 219 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 220 221 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 222 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 223 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 224 225 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 226 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 227 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 228 } 229 #endif 230 231 void bl2_plat_flush_bl31_params(void) 232 { 233 uint32_t product_cut, product, cut; 234 uint32_t boot_dev, boot_cpu; 235 uint32_t lcs, reg, val; 236 237 reg = mmio_read_32(RCAR_MODEMR); 238 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 239 240 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 241 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 242 emmc_terminate(); 243 244 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 245 bl2_secure_setting(); 246 247 reg = mmio_read_32(RCAR_PRR); 248 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 249 product = reg & PRR_PRODUCT_MASK; 250 cut = reg & PRR_CUT_MASK; 251 252 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 253 goto tlb; 254 255 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 256 goto tlb; 257 258 if (product == PRR_PRODUCT_D3) 259 goto tlb; 260 261 /* Disable MFIS write protection */ 262 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 263 264 tlb: 265 reg = mmio_read_32(RCAR_MODEMR); 266 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 267 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 268 boot_cpu != MODEMR_BOOT_CPU_CA53) 269 goto mmu; 270 271 if (product_cut == PRR_PRODUCT_H3_CUT20) { 272 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 273 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 275 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 276 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 277 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 278 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 279 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 280 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 281 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 282 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 283 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 284 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 285 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 286 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 287 } 288 289 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 290 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 291 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 292 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 293 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 294 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 295 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 296 297 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 298 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 299 } 300 301 mmu: 302 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 303 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 304 305 val = rcar_rom_get_lcs(&lcs); 306 if (val) { 307 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 308 panic(); 309 } 310 311 if (lcs == LCS_SE) 312 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 313 314 rcar_swdt_release(); 315 bl2_system_cpg_init(); 316 317 #if RCAR_BL2_DCACHE == 1 318 /* Disable data cache (clean and invalidate) */ 319 disable_mmu_el3(); 320 #endif 321 } 322 323 static uint32_t is_ddr_backup_mode(void) 324 { 325 #if RCAR_SYSTEM_SUSPEND 326 static uint32_t reason = RCAR_COLD_BOOT; 327 static uint32_t once; 328 329 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 330 uint8_t data; 331 #endif 332 if (once) 333 return reason; 334 335 once = 1; 336 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 337 return reason; 338 339 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 340 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 341 ERROR("BL2: REG Keep10 READ ERROR.\n"); 342 panic(); 343 } 344 345 if (KEEP10_MAGIC != data) 346 reason = RCAR_WARM_BOOT; 347 #else 348 reason = RCAR_WARM_BOOT; 349 #endif 350 return reason; 351 #else 352 return RCAR_COLD_BOOT; 353 #endif 354 } 355 356 int bl2_plat_handle_pre_image_load(unsigned int image_id) 357 { 358 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 359 bl_mem_params_node_t *bl_mem_params; 360 361 if (image_id != BL31_IMAGE_ID) 362 return 0; 363 364 bl_mem_params = get_bl_mem_params_node(image_id); 365 366 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 367 goto cold_boot; 368 369 *boot_kind = RCAR_WARM_BOOT; 370 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 371 372 console_flush(); 373 bl2_plat_flush_bl31_params(); 374 375 /* will not return */ 376 bl2_enter_bl31(&bl_mem_params->ep_info); 377 378 cold_boot: 379 *boot_kind = RCAR_COLD_BOOT; 380 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 381 382 return 0; 383 } 384 385 int bl2_plat_handle_post_image_load(unsigned int image_id) 386 { 387 static bl2_to_bl31_params_mem_t *params; 388 bl_mem_params_node_t *bl_mem_params; 389 390 if (!params) { 391 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 392 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 393 } 394 395 bl_mem_params = get_bl_mem_params_node(image_id); 396 397 switch (image_id) { 398 case BL31_IMAGE_ID: 399 break; 400 case BL32_IMAGE_ID: 401 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 402 sizeof(entry_point_info_t)); 403 break; 404 case BL33_IMAGE_ID: 405 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 406 sizeof(entry_point_info_t)); 407 break; 408 } 409 410 return 0; 411 } 412 413 struct meminfo *bl2_plat_sec_mem_layout(void) 414 { 415 return &bl2_tzram_layout; 416 } 417 418 static void bl2_populate_compatible_string(void *dt) 419 { 420 uint32_t board_type; 421 uint32_t board_rev; 422 uint32_t reg; 423 int ret; 424 425 fdt_setprop_u32(dt, 0, "#address-cells", 2); 426 fdt_setprop_u32(dt, 0, "#size-cells", 2); 427 428 /* Populate compatible string */ 429 rcar_get_board_type(&board_type, &board_rev); 430 switch (board_type) { 431 case BOARD_SALVATOR_X: 432 ret = fdt_setprop_string(dt, 0, "compatible", 433 "renesas,salvator-x"); 434 break; 435 case BOARD_SALVATOR_XS: 436 ret = fdt_setprop_string(dt, 0, "compatible", 437 "renesas,salvator-xs"); 438 break; 439 case BOARD_STARTER_KIT: 440 ret = fdt_setprop_string(dt, 0, "compatible", 441 "renesas,m3ulcb"); 442 break; 443 case BOARD_STARTER_KIT_PRE: 444 ret = fdt_setprop_string(dt, 0, "compatible", 445 "renesas,h3ulcb"); 446 break; 447 case BOARD_EAGLE: 448 ret = fdt_setprop_string(dt, 0, "compatible", 449 "renesas,eagle"); 450 break; 451 case BOARD_EBISU: 452 case BOARD_EBISU_4D: 453 ret = fdt_setprop_string(dt, 0, "compatible", 454 "renesas,ebisu"); 455 break; 456 case BOARD_DRAAK: 457 ret = fdt_setprop_string(dt, 0, "compatible", 458 "renesas,draak"); 459 break; 460 default: 461 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 462 panic(); 463 } 464 465 if (ret < 0) { 466 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 467 panic(); 468 } 469 470 reg = mmio_read_32(RCAR_PRR); 471 switch (reg & PRR_PRODUCT_MASK) { 472 case PRR_PRODUCT_H3: 473 ret = fdt_appendprop_string(dt, 0, "compatible", 474 "renesas,r8a7795"); 475 break; 476 case PRR_PRODUCT_M3: 477 ret = fdt_appendprop_string(dt, 0, "compatible", 478 "renesas,r8a7796"); 479 break; 480 case PRR_PRODUCT_M3N: 481 ret = fdt_appendprop_string(dt, 0, "compatible", 482 "renesas,r8a77965"); 483 break; 484 case PRR_PRODUCT_V3M: 485 ret = fdt_appendprop_string(dt, 0, "compatible", 486 "renesas,r8a77970"); 487 break; 488 case PRR_PRODUCT_E3: 489 ret = fdt_appendprop_string(dt, 0, "compatible", 490 "renesas,r8a77990"); 491 break; 492 case PRR_PRODUCT_D3: 493 ret = fdt_appendprop_string(dt, 0, "compatible", 494 "renesas,r8a77995"); 495 break; 496 default: 497 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 498 panic(); 499 } 500 501 if (ret < 0) { 502 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 503 panic(); 504 } 505 } 506 507 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 508 { 509 char nodename[32] = { 0 }; 510 uint64_t start, size; 511 uint64_t fdtsize; 512 int ret, node, chan; 513 514 for (chan = 0; chan < 4; chan++) { 515 start = dram_config[2 * chan]; 516 size = dram_config[2 * chan + 1]; 517 if (!size) 518 continue; 519 520 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 521 chan, start, start + size - 1, 522 (size >> 30) ? : size >> 20, 523 (size >> 30) ? "G" : "M"); 524 } 525 526 /* 527 * We add the DT nodes in reverse order here. The fdt_add_subnode() 528 * adds the DT node before the first existing DT node, so we have 529 * to add them in reverse order to get nodes sorted by address in 530 * the resulting DT. 531 */ 532 for (chan = 3; chan >= 0; chan--) { 533 start = dram_config[2 * chan]; 534 size = dram_config[2 * chan + 1]; 535 if (!size) 536 continue; 537 538 /* 539 * Channel 0 is mapped in 32bit space and the first 540 * 128 MiB are reserved 541 */ 542 if (chan == 0) { 543 start = 0x48000000; 544 size -= 0x8000000; 545 } 546 547 fdtsize = cpu_to_fdt64(size); 548 549 snprintf(nodename, sizeof(nodename), "memory@"); 550 unsigned_num_print(start, 16, nodename + strlen(nodename)); 551 node = ret = fdt_add_subnode(fdt, 0, nodename); 552 if (ret < 0) 553 goto err; 554 555 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 556 if (ret < 0) 557 goto err; 558 559 ret = fdt_setprop_u64(fdt, node, "reg", start); 560 if (ret < 0) 561 goto err; 562 563 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 564 sizeof(fdtsize)); 565 if (ret < 0) 566 goto err; 567 } 568 569 return; 570 err: 571 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 572 panic(); 573 } 574 575 static void bl2_advertise_dram_size(uint32_t product) 576 { 577 uint64_t dram_config[8] = { 578 [0] = 0x400000000ULL, 579 [2] = 0x500000000ULL, 580 [4] = 0x600000000ULL, 581 [6] = 0x700000000ULL, 582 }; 583 584 switch (product) { 585 case PRR_PRODUCT_H3: 586 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 587 /* 4GB(1GBx4) */ 588 dram_config[1] = 0x40000000ULL; 589 dram_config[3] = 0x40000000ULL; 590 dram_config[5] = 0x40000000ULL; 591 dram_config[7] = 0x40000000ULL; 592 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 593 (RCAR_DRAM_CHANNEL == 5) && \ 594 (RCAR_DRAM_SPLIT == 2) 595 /* 4GB(2GBx2 2ch split) */ 596 dram_config[1] = 0x80000000ULL; 597 dram_config[3] = 0x80000000ULL; 598 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 599 /* 8GB(2GBx4: default) */ 600 dram_config[1] = 0x80000000ULL; 601 dram_config[3] = 0x80000000ULL; 602 dram_config[5] = 0x80000000ULL; 603 dram_config[7] = 0x80000000ULL; 604 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 605 break; 606 607 case PRR_PRODUCT_M3: 608 #if (RCAR_GEN3_ULCB == 1) 609 /* 2GB(1GBx2 2ch split) */ 610 dram_config[1] = 0x40000000ULL; 611 dram_config[5] = 0x40000000ULL; 612 #else 613 /* 4GB(2GBx2 2ch split) */ 614 dram_config[1] = 0x80000000ULL; 615 dram_config[5] = 0x80000000ULL; 616 #endif 617 break; 618 619 case PRR_PRODUCT_M3N: 620 /* 2GB(1GBx2) */ 621 dram_config[1] = 0x80000000ULL; 622 break; 623 624 case PRR_PRODUCT_V3M: 625 /* 1GB(512MBx2) */ 626 dram_config[1] = 0x40000000ULL; 627 break; 628 629 case PRR_PRODUCT_E3: 630 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 631 /* 1GB(512MBx2) */ 632 dram_config[1] = 0x40000000ULL; 633 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 634 /* 2GB(512MBx4) */ 635 dram_config[1] = 0x80000000ULL; 636 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 637 /* 4GB(1GBx4) */ 638 dram_config[1] = 0x100000000ULL; 639 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 640 break; 641 642 case PRR_PRODUCT_D3: 643 /* 512MB */ 644 dram_config[1] = 0x20000000ULL; 645 break; 646 } 647 648 bl2_advertise_dram_entries(dram_config); 649 } 650 651 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 652 u_register_t arg3, u_register_t arg4) 653 { 654 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 655 uint32_t product, product_cut, major, minor; 656 int32_t ret; 657 const char *str; 658 const char *unknown = "unknown"; 659 const char *cpu_ca57 = "CA57"; 660 const char *cpu_ca53 = "CA53"; 661 const char *product_m3n = "M3N"; 662 const char *product_h3 = "H3"; 663 const char *product_m3 = "M3"; 664 const char *product_e3 = "E3"; 665 const char *product_d3 = "D3"; 666 const char *product_v3m = "V3M"; 667 const char *lcs_secure = "SE"; 668 const char *lcs_cm = "CM"; 669 const char *lcs_dm = "DM"; 670 const char *lcs_sd = "SD"; 671 const char *lcs_fa = "FA"; 672 const char *sscg_off = "PLL1 nonSSCG Clock select"; 673 const char *sscg_on = "PLL1 SSCG Clock select"; 674 const char *boot_hyper80 = "HyperFlash(80MHz)"; 675 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 676 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 677 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 678 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 679 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 680 const char *boot_hyper160 = "HyperFlash(150MHz)"; 681 #else 682 const char *boot_hyper160 = "HyperFlash(160MHz)"; 683 #endif 684 #if (RCAR_LOSSY_ENABLE == 1) 685 int fcnlnode; 686 #endif 687 688 bl2_init_generic_timer(); 689 690 reg = mmio_read_32(RCAR_MODEMR); 691 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 692 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 693 694 bl2_cpg_init(); 695 696 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 697 boot_cpu == MODEMR_BOOT_CPU_CA53) { 698 rcar_pfc_init(); 699 rcar_console_boot_init(); 700 } 701 702 plat_rcar_gic_driver_init(); 703 plat_rcar_gic_init(); 704 rcar_swdt_init(); 705 706 /* FIQ interrupts are taken to EL3 */ 707 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 708 709 write_daifclr(DAIF_FIQ_BIT); 710 711 reg = read_midr(); 712 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 713 switch (midr) { 714 case MIDR_CA57: 715 str = cpu_ca57; 716 break; 717 case MIDR_CA53: 718 str = cpu_ca53; 719 break; 720 default: 721 str = unknown; 722 break; 723 } 724 725 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 726 version_of_renesas); 727 728 reg = mmio_read_32(RCAR_PRR); 729 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 730 product = reg & PRR_PRODUCT_MASK; 731 732 switch (product) { 733 case PRR_PRODUCT_H3: 734 str = product_h3; 735 break; 736 case PRR_PRODUCT_M3: 737 str = product_m3; 738 break; 739 case PRR_PRODUCT_M3N: 740 str = product_m3n; 741 break; 742 case PRR_PRODUCT_V3M: 743 str = product_v3m; 744 break; 745 case PRR_PRODUCT_E3: 746 str = product_e3; 747 break; 748 case PRR_PRODUCT_D3: 749 str = product_d3; 750 break; 751 default: 752 str = unknown; 753 break; 754 } 755 756 if ((PRR_PRODUCT_M3 == product) && 757 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 758 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 759 /* M3 Ver.1.1 or Ver.1.2 */ 760 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 761 str); 762 } else { 763 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 764 str, 765 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 766 } 767 } else { 768 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 769 major = major + RCAR_MAJOR_OFFSET; 770 minor = reg & RCAR_MINOR_MASK; 771 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 772 } 773 774 if (product == PRR_PRODUCT_E3) { 775 reg = mmio_read_32(RCAR_MODEMR); 776 sscg = reg & RCAR_SSCG_MASK; 777 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 778 NOTICE("BL2: %s\n", str); 779 } 780 781 rcar_get_board_type(&type, &rev); 782 783 switch (type) { 784 case BOARD_SALVATOR_X: 785 case BOARD_KRIEK: 786 case BOARD_STARTER_KIT: 787 case BOARD_SALVATOR_XS: 788 case BOARD_EBISU: 789 case BOARD_STARTER_KIT_PRE: 790 case BOARD_EBISU_4D: 791 case BOARD_DRAAK: 792 case BOARD_EAGLE: 793 break; 794 default: 795 type = BOARD_UNKNOWN; 796 break; 797 } 798 799 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 800 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 801 else { 802 NOTICE("BL2: Board is %s Rev.%d.%d\n", 803 GET_BOARD_NAME(type), 804 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 805 } 806 807 #if RCAR_LSI != RCAR_AUTO 808 if (product != TARGET_PRODUCT) { 809 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 810 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 811 panic(); 812 } 813 #endif 814 rcar_avs_init(); 815 rcar_avs_setting(); 816 817 switch (boot_dev) { 818 case MODEMR_BOOT_DEV_HYPERFLASH160: 819 str = boot_hyper160; 820 break; 821 case MODEMR_BOOT_DEV_HYPERFLASH80: 822 str = boot_hyper80; 823 break; 824 case MODEMR_BOOT_DEV_QSPI_FLASH40: 825 str = boot_qspi40; 826 break; 827 case MODEMR_BOOT_DEV_QSPI_FLASH80: 828 str = boot_qspi80; 829 break; 830 case MODEMR_BOOT_DEV_EMMC_25X1: 831 #if RCAR_LSI == RCAR_D3 832 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 833 panic(); 834 #endif 835 str = boot_emmc25x1; 836 break; 837 case MODEMR_BOOT_DEV_EMMC_50X8: 838 #if RCAR_LSI == RCAR_D3 839 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 840 panic(); 841 #endif 842 str = boot_emmc50x8; 843 break; 844 default: 845 str = unknown; 846 break; 847 } 848 NOTICE("BL2: Boot device is %s\n", str); 849 850 rcar_avs_setting(); 851 reg = rcar_rom_get_lcs(&lcs); 852 if (reg) { 853 str = unknown; 854 goto lcm_state; 855 } 856 857 switch (lcs) { 858 case LCS_CM: 859 str = lcs_cm; 860 break; 861 case LCS_DM: 862 str = lcs_dm; 863 break; 864 case LCS_SD: 865 str = lcs_sd; 866 break; 867 case LCS_SE: 868 str = lcs_secure; 869 break; 870 case LCS_FA: 871 str = lcs_fa; 872 break; 873 default: 874 str = unknown; 875 break; 876 } 877 878 lcm_state: 879 NOTICE("BL2: LCM state is %s\n", str); 880 881 rcar_avs_end(); 882 is_ddr_backup_mode(); 883 884 bl2_tzram_layout.total_base = BL31_BASE; 885 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 886 887 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 888 boot_cpu == MODEMR_BOOT_CPU_CA53) { 889 ret = rcar_dram_init(); 890 if (ret) { 891 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 892 panic(); 893 } 894 rcar_qos_init(); 895 } 896 897 /* Set up FDT */ 898 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 899 if (ret) { 900 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 901 panic(); 902 } 903 904 /* Add platform compatible string */ 905 bl2_populate_compatible_string(fdt); 906 907 /* Print DRAM layout */ 908 bl2_advertise_dram_size(product); 909 910 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 911 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 912 if (rcar_emmc_init() != EMMC_SUCCESS) { 913 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 914 panic(); 915 } 916 rcar_emmc_memcard_power(EMMC_POWER_ON); 917 if (rcar_emmc_mount() != EMMC_SUCCESS) { 918 NOTICE("BL2: Failed to eMMC mount operation.\n"); 919 panic(); 920 } 921 } else { 922 rcar_rpc_init(); 923 rcar_dma_init(); 924 } 925 926 reg = mmio_read_32(RST_WDTRSTCR); 927 reg &= ~WDTRSTCR_RWDT_RSTMSK; 928 reg |= WDTRSTCR_PASSWORD; 929 mmio_write_32(RST_WDTRSTCR, reg); 930 931 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 932 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 933 934 reg = mmio_read_32(RCAR_PRR); 935 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 936 mmio_write_32(CPG_CA57DBGRCR, 937 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 938 939 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 940 mmio_write_32(CPG_CA53DBGRCR, 941 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 942 943 if (product_cut == PRR_PRODUCT_H3_CUT10) { 944 reg = mmio_read_32(CPG_PLL2CR); 945 reg &= ~((uint32_t) 1 << 5); 946 mmio_write_32(CPG_PLL2CR, reg); 947 948 reg = mmio_read_32(CPG_PLL4CR); 949 reg &= ~((uint32_t) 1 << 5); 950 mmio_write_32(CPG_PLL4CR, reg); 951 952 reg = mmio_read_32(CPG_PLL0CR); 953 reg &= ~((uint32_t) 1 << 12); 954 mmio_write_32(CPG_PLL0CR, reg); 955 } 956 #if (RCAR_LOSSY_ENABLE == 1) 957 NOTICE("BL2: Lossy Decomp areas\n"); 958 959 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 960 if (fcnlnode < 0) { 961 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 962 fcnlnode); 963 panic(); 964 } 965 966 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 967 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 968 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 969 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 970 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 971 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 972 #endif 973 974 fdt_pack(fdt); 975 NOTICE("BL2: FDT at %p\n", fdt); 976 977 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 978 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 979 rcar_io_emmc_setup(); 980 else 981 rcar_io_setup(); 982 } 983 984 void bl2_el3_plat_arch_setup(void) 985 { 986 #if RCAR_BL2_DCACHE == 1 987 NOTICE("BL2: D-Cache enable\n"); 988 rcar_configure_mmu_el3(BL2_BASE, 989 BL2_END - BL2_BASE, 990 BL2_RO_BASE, BL2_RO_LIMIT 991 #if USE_COHERENT_MEM 992 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 993 #endif 994 ); 995 #endif 996 } 997 998 void bl2_platform_setup(void) 999 { 1000 1001 } 1002 1003 static void bl2_init_generic_timer(void) 1004 { 1005 /* FIXME: V3M 16.666 MHz ? */ 1006 #if RCAR_LSI == RCAR_D3 1007 uint32_t reg_cntfid = EXTAL_DRAAK; 1008 #elif RCAR_LSI == RCAR_E3 1009 uint32_t reg_cntfid = EXTAL_EBISU; 1010 #else /* RCAR_LSI == RCAR_E3 */ 1011 uint32_t reg; 1012 uint32_t reg_cntfid; 1013 uint32_t modemr; 1014 uint32_t modemr_pll; 1015 uint32_t board_type; 1016 uint32_t board_rev; 1017 uint32_t pll_table[] = { 1018 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1019 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1020 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1021 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1022 }; 1023 1024 modemr = mmio_read_32(RCAR_MODEMR); 1025 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1026 1027 /* Set frequency data in CNTFID0 */ 1028 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1029 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1030 switch (modemr_pll) { 1031 case MD14_MD13_TYPE_0: 1032 rcar_get_board_type(&board_type, &board_rev); 1033 if (BOARD_SALVATOR_XS == board_type) { 1034 reg_cntfid = EXTAL_SALVATOR_XS; 1035 } 1036 break; 1037 case MD14_MD13_TYPE_3: 1038 if (PRR_PRODUCT_H3_CUT10 == reg) { 1039 reg_cntfid = reg_cntfid >> 1U; 1040 } 1041 break; 1042 default: 1043 /* none */ 1044 break; 1045 } 1046 #endif /* RCAR_LSI == RCAR_E3 */ 1047 /* Update memory mapped and register based freqency */ 1048 write_cntfrq_el0((u_register_t )reg_cntfid); 1049 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1050 /* Enable counter */ 1051 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1052 (uint32_t)CNTCR_EN); 1053 } 1054