1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 44 45 #if USE_COHERENT_MEM 46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 48 #endif 49 50 extern void plat_rcar_gic_driver_init(void); 51 extern void plat_rcar_gic_init(void); 52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 53 extern void bl2_system_cpg_init(void); 54 extern void bl2_secure_setting(void); 55 extern void bl2_cpg_init(void); 56 extern void rcar_io_emmc_setup(void); 57 extern void rcar_io_setup(void); 58 extern void rcar_swdt_release(void); 59 extern void rcar_swdt_init(void); 60 extern void rcar_rpc_init(void); 61 extern void rcar_pfc_init(void); 62 extern void rcar_dma_init(void); 63 64 /* R-Car Gen3 product check */ 65 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 66 #define TARGET_PRODUCT RCAR_PRODUCT_H3 67 #define TARGET_NAME "R-Car H3" 68 #elif RCAR_LSI == RCAR_M3 69 #define TARGET_PRODUCT RCAR_PRODUCT_M3 70 #define TARGET_NAME "R-Car M3" 71 #elif RCAR_LSI == RCAR_M3N 72 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 73 #define TARGET_NAME "R-Car M3N" 74 #elif RCAR_LSI == RCAR_E3 75 #define TARGET_PRODUCT RCAR_PRODUCT_E3 76 #define TARGET_NAME "R-Car E3" 77 #elif RCAR_LSI == RCAR_AUTO 78 #define TARGET_NAME "R-Car H3/M3/M3N" 79 #endif 80 81 #if (RCAR_LSI == RCAR_E3) 82 #define GPIO_INDT (GPIO_INDT6) 83 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 84 #else 85 #define GPIO_INDT (GPIO_INDT1) 86 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 87 #endif 88 89 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 90 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 91 assert_bl31_params_do_not_fit_in_shared_memory); 92 93 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 94 95 /* FDT with DRAM configuration */ 96 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 97 static void *fdt = (void *)fdt_blob; 98 99 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 100 char *string) 101 { 102 /* Just need enough space to store 64 bit decimal integer */ 103 char num_buf[20]; 104 int i = 0; 105 unsigned int rem; 106 107 do { 108 rem = unum % radix; 109 if (rem < 0xa) 110 num_buf[i] = '0' + rem; 111 else 112 num_buf[i] = 'a' + (rem - 0xa); 113 i++; 114 unum /= radix; 115 } while (unum > 0U); 116 117 while (--i >= 0) 118 *string++ = num_buf[i]; 119 } 120 121 #if (RCAR_LOSSY_ENABLE == 1) 122 typedef struct bl2_lossy_info { 123 uint32_t magic; 124 uint32_t a0; 125 uint32_t b0; 126 } bl2_lossy_info_t; 127 128 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 129 uint64_t end_addr, uint32_t format, 130 uint32_t enable, int fcnlnode) 131 { 132 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 133 char nodename[40] = { 0 }; 134 int ret, node; 135 136 /* Ignore undefined addresses */ 137 if (start_addr == 0 && end_addr == 0) 138 return; 139 140 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 141 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 142 143 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 144 if (ret < 0) { 145 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 146 panic(); 147 } 148 149 ret = fdt_setprop_string(fdt, node, "compatible", 150 "renesas,lossy-decompression"); 151 if (ret < 0) { 152 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 153 panic(); 154 } 155 156 ret = fdt_appendprop_string(fdt, node, "compatible", 157 "shared-dma-pool"); 158 if (ret < 0) { 159 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 160 panic(); 161 } 162 163 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 164 if (ret < 0) { 165 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 166 panic(); 167 } 168 169 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 170 if (ret < 0) { 171 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 172 panic(); 173 } 174 175 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 176 if (ret < 0) { 177 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 178 panic(); 179 } 180 181 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 182 if (ret < 0) { 183 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 184 panic(); 185 } 186 } 187 188 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 189 uint64_t end_addr, uint32_t format, 190 uint32_t enable, int fcnlnode) 191 { 192 bl2_lossy_info_t info; 193 uint32_t reg; 194 195 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 196 197 reg = format | (start_addr >> 20); 198 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 199 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 200 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 201 202 info.magic = 0x12345678U; 203 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 204 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 205 206 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 207 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 208 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 209 210 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 211 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 212 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 213 } 214 #endif 215 216 void bl2_plat_flush_bl31_params(void) 217 { 218 uint32_t product_cut, product, cut; 219 uint32_t boot_dev, boot_cpu; 220 uint32_t lcs, reg, val; 221 222 reg = mmio_read_32(RCAR_MODEMR); 223 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 224 225 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 226 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 227 emmc_terminate(); 228 229 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 230 bl2_secure_setting(); 231 232 reg = mmio_read_32(RCAR_PRR); 233 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 234 product = reg & RCAR_PRODUCT_MASK; 235 cut = reg & RCAR_CUT_MASK; 236 237 if (product == RCAR_PRODUCT_M3) 238 goto tlb; 239 240 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 241 goto tlb; 242 243 /* Disable MFIS write protection */ 244 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 245 246 tlb: 247 reg = mmio_read_32(RCAR_MODEMR); 248 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 249 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 250 boot_cpu != MODEMR_BOOT_CPU_CA53) 251 goto mmu; 252 253 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 254 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 255 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 256 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 257 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 258 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 259 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 260 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 261 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 262 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 263 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 264 } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || 265 (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { 266 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 267 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 268 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 269 } 270 271 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 272 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 273 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 274 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 275 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 276 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 277 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 278 279 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 280 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 281 } 282 283 mmu: 284 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 285 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 286 287 val = rcar_rom_get_lcs(&lcs); 288 if (val) { 289 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 290 panic(); 291 } 292 293 if (lcs == LCS_SE) 294 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 295 296 rcar_swdt_release(); 297 bl2_system_cpg_init(); 298 299 #if RCAR_BL2_DCACHE == 1 300 /* Disable data cache (clean and invalidate) */ 301 disable_mmu_el3(); 302 #endif 303 } 304 305 static uint32_t is_ddr_backup_mode(void) 306 { 307 #if RCAR_SYSTEM_SUSPEND 308 static uint32_t reason = RCAR_COLD_BOOT; 309 static uint32_t once; 310 311 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 312 uint8_t data; 313 #endif 314 if (once) 315 return reason; 316 317 once = 1; 318 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 319 return reason; 320 321 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 322 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 323 ERROR("BL2: REG Keep10 READ ERROR.\n"); 324 panic(); 325 } 326 327 if (KEEP10_MAGIC != data) 328 reason = RCAR_WARM_BOOT; 329 #else 330 reason = RCAR_WARM_BOOT; 331 #endif 332 return reason; 333 #else 334 return RCAR_COLD_BOOT; 335 #endif 336 } 337 338 int bl2_plat_handle_pre_image_load(unsigned int image_id) 339 { 340 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 341 bl_mem_params_node_t *bl_mem_params; 342 343 if (image_id != BL31_IMAGE_ID) 344 return 0; 345 346 bl_mem_params = get_bl_mem_params_node(image_id); 347 348 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 349 goto cold_boot; 350 351 *boot_kind = RCAR_WARM_BOOT; 352 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 353 354 console_flush(); 355 bl2_plat_flush_bl31_params(); 356 357 /* will not return */ 358 bl2_enter_bl31(&bl_mem_params->ep_info); 359 360 cold_boot: 361 *boot_kind = RCAR_COLD_BOOT; 362 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 363 364 return 0; 365 } 366 367 int bl2_plat_handle_post_image_load(unsigned int image_id) 368 { 369 static bl2_to_bl31_params_mem_t *params; 370 bl_mem_params_node_t *bl_mem_params; 371 372 if (!params) { 373 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 374 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 375 } 376 377 bl_mem_params = get_bl_mem_params_node(image_id); 378 379 switch (image_id) { 380 case BL31_IMAGE_ID: 381 break; 382 case BL32_IMAGE_ID: 383 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 384 sizeof(entry_point_info_t)); 385 break; 386 case BL33_IMAGE_ID: 387 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 388 sizeof(entry_point_info_t)); 389 break; 390 } 391 392 return 0; 393 } 394 395 struct meminfo *bl2_plat_sec_mem_layout(void) 396 { 397 return &bl2_tzram_layout; 398 } 399 400 static void bl2_populate_compatible_string(void *fdt) 401 { 402 uint32_t board_type; 403 uint32_t board_rev; 404 uint32_t reg; 405 int ret; 406 407 /* Populate compatible string */ 408 rcar_get_board_type(&board_type, &board_rev); 409 switch (board_type) { 410 case BOARD_SALVATOR_X: 411 ret = fdt_setprop_string(fdt, 0, "compatible", 412 "renesas,salvator-x"); 413 break; 414 case BOARD_SALVATOR_XS: 415 ret = fdt_setprop_string(fdt, 0, "compatible", 416 "renesas,salvator-xs"); 417 break; 418 case BOARD_STARTER_KIT: 419 ret = fdt_setprop_string(fdt, 0, "compatible", 420 "renesas,m3ulcb"); 421 break; 422 case BOARD_STARTER_KIT_PRE: 423 ret = fdt_setprop_string(fdt, 0, "compatible", 424 "renesas,h3ulcb"); 425 break; 426 case BOARD_EBISU: 427 case BOARD_EBISU_4D: 428 ret = fdt_setprop_string(fdt, 0, "compatible", 429 "renesas,ebisu"); 430 break; 431 default: 432 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 433 panic(); 434 } 435 436 if (ret < 0) { 437 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 438 panic(); 439 } 440 441 reg = mmio_read_32(RCAR_PRR); 442 switch (reg & RCAR_PRODUCT_MASK) { 443 case RCAR_PRODUCT_H3: 444 ret = fdt_appendprop_string(fdt, 0, "compatible", 445 "renesas,r8a7795"); 446 break; 447 case RCAR_PRODUCT_M3: 448 ret = fdt_appendprop_string(fdt, 0, "compatible", 449 "renesas,r8a7796"); 450 break; 451 case RCAR_PRODUCT_M3N: 452 ret = fdt_appendprop_string(fdt, 0, "compatible", 453 "renesas,r8a77965"); 454 break; 455 case RCAR_PRODUCT_E3: 456 ret = fdt_appendprop_string(fdt, 0, "compatible", 457 "renesas,r8a77990"); 458 break; 459 default: 460 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 461 panic(); 462 } 463 464 if (ret < 0) { 465 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 466 panic(); 467 } 468 } 469 470 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 471 { 472 char nodename[32] = { 0 }; 473 uint64_t start, size; 474 uint64_t fdtsize; 475 int ret, node, chan; 476 477 for (chan = 0; chan < 4; chan++) { 478 start = dram_config[2 * chan]; 479 size = dram_config[2 * chan + 1]; 480 if (!size) 481 continue; 482 483 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 484 chan, start, start + size - 1, size >> 30); 485 } 486 487 /* 488 * We add the DT nodes in reverse order here. The fdt_add_subnode() 489 * adds the DT node before the first existing DT node, so we have 490 * to add them in reverse order to get nodes sorted by address in 491 * the resulting DT. 492 */ 493 for (chan = 3; chan >= 0; chan--) { 494 start = dram_config[2 * chan]; 495 size = dram_config[2 * chan + 1]; 496 if (!size) 497 continue; 498 499 /* 500 * Channel 0 is mapped in 32bit space and the first 501 * 128 MiB are reserved 502 */ 503 if (chan == 0) { 504 start = 0x48000000; 505 size -= 0x8000000; 506 } 507 508 fdtsize = cpu_to_fdt64(size); 509 510 snprintf(nodename, sizeof(nodename), "memory@"); 511 unsigned_num_print(start, 16, nodename + strlen(nodename)); 512 node = ret = fdt_add_subnode(fdt, 0, nodename); 513 if (ret < 0) 514 goto err; 515 516 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 517 if (ret < 0) 518 goto err; 519 520 ret = fdt_setprop_u64(fdt, node, "reg", start); 521 if (ret < 0) 522 goto err; 523 524 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 525 sizeof(fdtsize)); 526 if (ret < 0) 527 goto err; 528 } 529 530 return; 531 err: 532 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 533 panic(); 534 } 535 536 static void bl2_advertise_dram_size(uint32_t product) 537 { 538 uint64_t dram_config[8] = { 539 [0] = 0x400000000ULL, 540 [2] = 0x500000000ULL, 541 [4] = 0x600000000ULL, 542 [6] = 0x700000000ULL, 543 }; 544 545 switch (product) { 546 case RCAR_PRODUCT_H3: 547 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 548 /* 4GB(1GBx4) */ 549 dram_config[1] = 0x40000000ULL; 550 dram_config[3] = 0x40000000ULL; 551 dram_config[5] = 0x40000000ULL; 552 dram_config[7] = 0x40000000ULL; 553 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 554 (RCAR_DRAM_CHANNEL == 5) && \ 555 (RCAR_DRAM_SPLIT == 2) 556 /* 4GB(2GBx2 2ch split) */ 557 dram_config[1] = 0x80000000ULL; 558 dram_config[3] = 0x80000000ULL; 559 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 560 /* 8GB(2GBx4: default) */ 561 dram_config[1] = 0x80000000ULL; 562 dram_config[3] = 0x80000000ULL; 563 dram_config[5] = 0x80000000ULL; 564 dram_config[7] = 0x80000000ULL; 565 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 566 break; 567 568 case RCAR_PRODUCT_M3: 569 /* 4GB(2GBx2 2ch split) */ 570 dram_config[1] = 0x80000000ULL; 571 dram_config[5] = 0x80000000ULL; 572 break; 573 574 case RCAR_PRODUCT_M3N: 575 /* 2GB(1GBx2) */ 576 dram_config[1] = 0x80000000ULL; 577 break; 578 579 case RCAR_PRODUCT_E3: 580 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 581 /* 1GB(512MBx2) */ 582 dram_config[1] = 0x40000000ULL; 583 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 584 /* 2GB(512MBx4) */ 585 dram_config[1] = 0x80000000ULL; 586 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 587 /* 4GB(1GBx4) */ 588 dram_config[1] = 0x100000000ULL; 589 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 590 break; 591 } 592 593 bl2_advertise_dram_entries(dram_config); 594 } 595 596 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 597 u_register_t arg3, u_register_t arg4) 598 { 599 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 600 uint32_t product, product_cut, major, minor; 601 int32_t ret; 602 const char *str; 603 const char *unknown = "unknown"; 604 const char *cpu_ca57 = "CA57"; 605 const char *cpu_ca53 = "CA53"; 606 const char *product_m3n = "M3N"; 607 const char *product_h3 = "H3"; 608 const char *product_m3 = "M3"; 609 const char *product_e3 = "E3"; 610 const char *lcs_secure = "SE"; 611 const char *lcs_cm = "CM"; 612 const char *lcs_dm = "DM"; 613 const char *lcs_sd = "SD"; 614 const char *lcs_fa = "FA"; 615 const char *sscg_off = "PLL1 nonSSCG Clock select"; 616 const char *sscg_on = "PLL1 SSCG Clock select"; 617 const char *boot_hyper80 = "HyperFlash(80MHz)"; 618 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 619 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 620 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 621 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 622 #if RCAR_LSI == RCAR_E3 623 const char *boot_hyper160 = "HyperFlash(150MHz)"; 624 #else 625 const char *boot_hyper160 = "HyperFlash(160MHz)"; 626 #endif 627 #if (RCAR_LOSSY_ENABLE == 1) 628 int fcnlnode; 629 #endif 630 631 reg = mmio_read_32(RCAR_MODEMR); 632 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 633 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 634 635 bl2_cpg_init(); 636 637 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 638 boot_cpu == MODEMR_BOOT_CPU_CA53) { 639 rcar_pfc_init(); 640 /* console configuration (platform specific) done in driver */ 641 console_init(0, 0, 0); 642 } 643 644 plat_rcar_gic_driver_init(); 645 plat_rcar_gic_init(); 646 rcar_swdt_init(); 647 648 /* FIQ interrupts are taken to EL3 */ 649 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 650 651 write_daifclr(DAIF_FIQ_BIT); 652 653 reg = read_midr(); 654 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 655 switch (midr) { 656 case MIDR_CA57: 657 str = cpu_ca57; 658 break; 659 case MIDR_CA53: 660 str = cpu_ca53; 661 break; 662 default: 663 str = unknown; 664 break; 665 } 666 667 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 668 version_of_renesas); 669 670 reg = mmio_read_32(RCAR_PRR); 671 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 672 product = reg & RCAR_PRODUCT_MASK; 673 674 switch (product) { 675 case RCAR_PRODUCT_H3: 676 str = product_h3; 677 break; 678 case RCAR_PRODUCT_M3: 679 str = product_m3; 680 break; 681 case RCAR_PRODUCT_M3N: 682 str = product_m3n; 683 break; 684 case RCAR_PRODUCT_E3: 685 str = product_e3; 686 break; 687 default: 688 str = unknown; 689 break; 690 } 691 692 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 693 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 694 } else { 695 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 696 major = major + RCAR_MAJOR_OFFSET; 697 minor = reg & RCAR_MINOR_MASK; 698 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 699 } 700 701 if (product == RCAR_PRODUCT_E3) { 702 reg = mmio_read_32(RCAR_MODEMR); 703 sscg = reg & RCAR_SSCG_MASK; 704 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 705 NOTICE("BL2: %s\n", str); 706 } 707 708 rcar_get_board_type(&type, &rev); 709 710 switch (type) { 711 case BOARD_SALVATOR_X: 712 case BOARD_KRIEK: 713 case BOARD_STARTER_KIT: 714 case BOARD_SALVATOR_XS: 715 case BOARD_EBISU: 716 case BOARD_STARTER_KIT_PRE: 717 case BOARD_EBISU_4D: 718 break; 719 default: 720 type = BOARD_UNKNOWN; 721 break; 722 } 723 724 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 725 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 726 else { 727 NOTICE("BL2: Board is %s Rev.%d.%d\n", 728 GET_BOARD_NAME(type), 729 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 730 } 731 732 #if RCAR_LSI != RCAR_AUTO 733 if (product != TARGET_PRODUCT) { 734 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 735 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 736 panic(); 737 } 738 #endif 739 rcar_avs_init(); 740 rcar_avs_setting(); 741 742 switch (boot_dev) { 743 case MODEMR_BOOT_DEV_HYPERFLASH160: 744 str = boot_hyper160; 745 break; 746 case MODEMR_BOOT_DEV_HYPERFLASH80: 747 str = boot_hyper80; 748 break; 749 case MODEMR_BOOT_DEV_QSPI_FLASH40: 750 str = boot_qspi40; 751 break; 752 case MODEMR_BOOT_DEV_QSPI_FLASH80: 753 str = boot_qspi80; 754 break; 755 case MODEMR_BOOT_DEV_EMMC_25X1: 756 str = boot_emmc25x1; 757 break; 758 case MODEMR_BOOT_DEV_EMMC_50X8: 759 str = boot_emmc50x8; 760 break; 761 default: 762 str = unknown; 763 break; 764 } 765 NOTICE("BL2: Boot device is %s\n", str); 766 767 rcar_avs_setting(); 768 reg = rcar_rom_get_lcs(&lcs); 769 if (reg) { 770 str = unknown; 771 goto lcm_state; 772 } 773 774 switch (lcs) { 775 case LCS_CM: 776 str = lcs_cm; 777 break; 778 case LCS_DM: 779 str = lcs_dm; 780 break; 781 case LCS_SD: 782 str = lcs_sd; 783 break; 784 case LCS_SE: 785 str = lcs_secure; 786 break; 787 case LCS_FA: 788 str = lcs_fa; 789 break; 790 default: 791 str = unknown; 792 break; 793 } 794 795 lcm_state: 796 NOTICE("BL2: LCM state is %s\n", str); 797 798 rcar_avs_end(); 799 is_ddr_backup_mode(); 800 801 bl2_tzram_layout.total_base = BL31_BASE; 802 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 803 804 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 805 boot_cpu == MODEMR_BOOT_CPU_CA53) { 806 ret = rcar_dram_init(); 807 if (ret) { 808 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 809 panic(); 810 } 811 rcar_qos_init(); 812 } 813 814 /* Set up FDT */ 815 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 816 if (ret) { 817 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 818 panic(); 819 } 820 821 /* Add platform compatible string */ 822 bl2_populate_compatible_string(fdt); 823 824 /* Print DRAM layout */ 825 bl2_advertise_dram_size(product); 826 827 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 828 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 829 if (rcar_emmc_init() != EMMC_SUCCESS) { 830 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 831 panic(); 832 } 833 rcar_emmc_memcard_power(EMMC_POWER_ON); 834 if (rcar_emmc_mount() != EMMC_SUCCESS) { 835 NOTICE("BL2: Failed to eMMC mount operation.\n"); 836 panic(); 837 } 838 } else { 839 rcar_rpc_init(); 840 rcar_dma_init(); 841 } 842 843 reg = mmio_read_32(RST_WDTRSTCR); 844 reg &= ~WDTRSTCR_RWDT_RSTMSK; 845 reg |= WDTRSTCR_PASSWORD; 846 mmio_write_32(RST_WDTRSTCR, reg); 847 848 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 849 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 850 851 reg = mmio_read_32(RCAR_PRR); 852 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 853 mmio_write_32(CPG_CA57DBGRCR, 854 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 855 856 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 857 mmio_write_32(CPG_CA53DBGRCR, 858 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 859 860 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 861 reg = mmio_read_32(CPG_PLL2CR); 862 reg &= ~((uint32_t) 1 << 5); 863 mmio_write_32(CPG_PLL2CR, reg); 864 865 reg = mmio_read_32(CPG_PLL4CR); 866 reg &= ~((uint32_t) 1 << 5); 867 mmio_write_32(CPG_PLL4CR, reg); 868 869 reg = mmio_read_32(CPG_PLL0CR); 870 reg &= ~((uint32_t) 1 << 12); 871 mmio_write_32(CPG_PLL0CR, reg); 872 } 873 #if (RCAR_LOSSY_ENABLE == 1) 874 NOTICE("BL2: Lossy Decomp areas\n"); 875 876 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 877 if (fcnlnode < 0) { 878 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 879 fcnlnode); 880 panic(); 881 } 882 883 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 884 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 885 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 886 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 887 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 888 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 889 #endif 890 891 fdt_pack(fdt); 892 NOTICE("BL2: FDT at %p\n", fdt); 893 894 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 895 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 896 rcar_io_emmc_setup(); 897 else 898 rcar_io_setup(); 899 } 900 901 void bl2_el3_plat_arch_setup(void) 902 { 903 #if RCAR_BL2_DCACHE == 1 904 NOTICE("BL2: D-Cache enable\n"); 905 rcar_configure_mmu_el3(BL2_BASE, 906 BL2_END - BL2_BASE, 907 BL2_RO_BASE, BL2_RO_LIMIT 908 #if USE_COHERENT_MEM 909 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 910 #endif 911 ); 912 #endif 913 } 914 915 void bl2_platform_setup(void) 916 { 917 918 } 919