1 /* 2 * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 44 45 #if USE_COHERENT_MEM 46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 48 #endif 49 50 extern void plat_rcar_gic_driver_init(void); 51 extern void plat_rcar_gic_init(void); 52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 53 extern void bl2_system_cpg_init(void); 54 extern void bl2_secure_setting(void); 55 extern void bl2_cpg_init(void); 56 extern void rcar_io_emmc_setup(void); 57 extern void rcar_io_setup(void); 58 extern void rcar_swdt_release(void); 59 extern void rcar_swdt_init(void); 60 extern void rcar_rpc_init(void); 61 extern void rcar_pfc_init(void); 62 extern void rcar_dma_init(void); 63 64 static void bl2_init_generic_timer(void); 65 66 /* R-Car Gen3 product check */ 67 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 68 #define TARGET_PRODUCT PRR_PRODUCT_H3 69 #define TARGET_NAME "R-Car H3" 70 #elif RCAR_LSI == RCAR_M3 71 #define TARGET_PRODUCT PRR_PRODUCT_M3 72 #define TARGET_NAME "R-Car M3" 73 #elif RCAR_LSI == RCAR_M3N 74 #define TARGET_PRODUCT PRR_PRODUCT_M3N 75 #define TARGET_NAME "R-Car M3N" 76 #elif RCAR_LSI == RCAR_V3M 77 #define TARGET_PRODUCT PRR_PRODUCT_V3M 78 #define TARGET_NAME "R-Car V3M" 79 #elif RCAR_LSI == RCAR_E3 80 #define TARGET_PRODUCT PRR_PRODUCT_E3 81 #define TARGET_NAME "R-Car E3" 82 #elif RCAR_LSI == RCAR_D3 83 #define TARGET_PRODUCT PRR_PRODUCT_D3 84 #define TARGET_NAME "R-Car D3" 85 #elif RCAR_LSI == RCAR_AUTO 86 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 87 #endif 88 89 #if (RCAR_LSI == RCAR_E3) 90 #define GPIO_INDT (GPIO_INDT6) 91 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 92 #else 93 #define GPIO_INDT (GPIO_INDT1) 94 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 95 #endif 96 97 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 98 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 99 assert_bl31_params_do_not_fit_in_shared_memory); 100 101 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 102 103 /* FDT with DRAM configuration */ 104 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 105 static void *fdt = (void *)fdt_blob; 106 107 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 108 char *string) 109 { 110 /* Just need enough space to store 64 bit decimal integer */ 111 char num_buf[20]; 112 int i = 0; 113 unsigned int rem; 114 115 do { 116 rem = unum % radix; 117 if (rem < 0xa) 118 num_buf[i] = '0' + rem; 119 else 120 num_buf[i] = 'a' + (rem - 0xa); 121 i++; 122 unum /= radix; 123 } while (unum > 0U); 124 125 while (--i >= 0) 126 *string++ = num_buf[i]; 127 } 128 129 #if (RCAR_LOSSY_ENABLE == 1) 130 typedef struct bl2_lossy_info { 131 uint32_t magic; 132 uint32_t a0; 133 uint32_t b0; 134 } bl2_lossy_info_t; 135 136 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 137 uint64_t end_addr, uint32_t format, 138 uint32_t enable, int fcnlnode) 139 { 140 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 141 char nodename[40] = { 0 }; 142 int ret, node; 143 144 /* Ignore undefined addresses */ 145 if (start_addr == 0 && end_addr == 0) 146 return; 147 148 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 149 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 150 151 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 152 if (ret < 0) { 153 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 154 panic(); 155 } 156 157 ret = fdt_setprop_string(fdt, node, "compatible", 158 "renesas,lossy-decompression"); 159 if (ret < 0) { 160 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 161 panic(); 162 } 163 164 ret = fdt_appendprop_string(fdt, node, "compatible", 165 "shared-dma-pool"); 166 if (ret < 0) { 167 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 168 panic(); 169 } 170 171 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 172 if (ret < 0) { 173 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 174 panic(); 175 } 176 177 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 178 if (ret < 0) { 179 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 180 panic(); 181 } 182 183 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 184 if (ret < 0) { 185 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 186 panic(); 187 } 188 189 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 190 if (ret < 0) { 191 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 192 panic(); 193 } 194 } 195 196 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 197 uint64_t end_addr, uint32_t format, 198 uint32_t enable, int fcnlnode) 199 { 200 bl2_lossy_info_t info; 201 uint32_t reg; 202 203 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 204 205 reg = format | (start_addr >> 20); 206 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 207 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 208 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 209 210 info.magic = 0x12345678U; 211 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 212 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 213 214 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 215 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 216 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 217 218 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 219 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 220 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 221 } 222 #endif 223 224 void bl2_plat_flush_bl31_params(void) 225 { 226 uint32_t product_cut, product, cut; 227 uint32_t boot_dev, boot_cpu; 228 uint32_t lcs, reg, val; 229 230 reg = mmio_read_32(RCAR_MODEMR); 231 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 232 233 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 234 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 235 emmc_terminate(); 236 237 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 238 bl2_secure_setting(); 239 240 reg = mmio_read_32(RCAR_PRR); 241 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 242 product = reg & PRR_PRODUCT_MASK; 243 cut = reg & PRR_CUT_MASK; 244 245 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 246 goto tlb; 247 248 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 249 goto tlb; 250 251 if (product == PRR_PRODUCT_D3) 252 goto tlb; 253 254 /* Disable MFIS write protection */ 255 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 256 257 tlb: 258 reg = mmio_read_32(RCAR_MODEMR); 259 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 260 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 261 boot_cpu != MODEMR_BOOT_CPU_CA53) 262 goto mmu; 263 264 if (product_cut == PRR_PRODUCT_H3_CUT20) { 265 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 266 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 267 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 268 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 269 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 270 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 271 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 272 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 273 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 275 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 276 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 277 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 278 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 280 } 281 282 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 283 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 284 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 285 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 286 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 287 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 288 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 289 290 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 291 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 292 } 293 294 mmu: 295 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 296 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 297 298 val = rcar_rom_get_lcs(&lcs); 299 if (val) { 300 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 301 panic(); 302 } 303 304 if (lcs == LCS_SE) 305 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 306 307 rcar_swdt_release(); 308 bl2_system_cpg_init(); 309 310 #if RCAR_BL2_DCACHE == 1 311 /* Disable data cache (clean and invalidate) */ 312 disable_mmu_el3(); 313 #endif 314 } 315 316 static uint32_t is_ddr_backup_mode(void) 317 { 318 #if RCAR_SYSTEM_SUSPEND 319 static uint32_t reason = RCAR_COLD_BOOT; 320 static uint32_t once; 321 322 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 323 uint8_t data; 324 #endif 325 if (once) 326 return reason; 327 328 once = 1; 329 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 330 return reason; 331 332 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 333 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 334 ERROR("BL2: REG Keep10 READ ERROR.\n"); 335 panic(); 336 } 337 338 if (KEEP10_MAGIC != data) 339 reason = RCAR_WARM_BOOT; 340 #else 341 reason = RCAR_WARM_BOOT; 342 #endif 343 return reason; 344 #else 345 return RCAR_COLD_BOOT; 346 #endif 347 } 348 349 int bl2_plat_handle_pre_image_load(unsigned int image_id) 350 { 351 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 352 bl_mem_params_node_t *bl_mem_params; 353 354 if (image_id != BL31_IMAGE_ID) 355 return 0; 356 357 bl_mem_params = get_bl_mem_params_node(image_id); 358 359 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 360 goto cold_boot; 361 362 *boot_kind = RCAR_WARM_BOOT; 363 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 364 365 console_flush(); 366 bl2_plat_flush_bl31_params(); 367 368 /* will not return */ 369 bl2_enter_bl31(&bl_mem_params->ep_info); 370 371 cold_boot: 372 *boot_kind = RCAR_COLD_BOOT; 373 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 374 375 return 0; 376 } 377 378 int bl2_plat_handle_post_image_load(unsigned int image_id) 379 { 380 static bl2_to_bl31_params_mem_t *params; 381 bl_mem_params_node_t *bl_mem_params; 382 383 if (!params) { 384 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 385 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 386 } 387 388 bl_mem_params = get_bl_mem_params_node(image_id); 389 390 switch (image_id) { 391 case BL31_IMAGE_ID: 392 break; 393 case BL32_IMAGE_ID: 394 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 395 sizeof(entry_point_info_t)); 396 break; 397 case BL33_IMAGE_ID: 398 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 399 sizeof(entry_point_info_t)); 400 break; 401 } 402 403 return 0; 404 } 405 406 struct meminfo *bl2_plat_sec_mem_layout(void) 407 { 408 return &bl2_tzram_layout; 409 } 410 411 static void bl2_populate_compatible_string(void *dt) 412 { 413 uint32_t board_type; 414 uint32_t board_rev; 415 uint32_t reg; 416 int ret; 417 418 fdt_setprop_u32(dt, 0, "#address-cells", 2); 419 fdt_setprop_u32(dt, 0, "#size-cells", 2); 420 421 /* Populate compatible string */ 422 rcar_get_board_type(&board_type, &board_rev); 423 switch (board_type) { 424 case BOARD_SALVATOR_X: 425 ret = fdt_setprop_string(dt, 0, "compatible", 426 "renesas,salvator-x"); 427 break; 428 case BOARD_SALVATOR_XS: 429 ret = fdt_setprop_string(dt, 0, "compatible", 430 "renesas,salvator-xs"); 431 break; 432 case BOARD_STARTER_KIT: 433 ret = fdt_setprop_string(dt, 0, "compatible", 434 "renesas,m3ulcb"); 435 break; 436 case BOARD_STARTER_KIT_PRE: 437 ret = fdt_setprop_string(dt, 0, "compatible", 438 "renesas,h3ulcb"); 439 break; 440 case BOARD_EAGLE: 441 ret = fdt_setprop_string(dt, 0, "compatible", 442 "renesas,eagle"); 443 break; 444 case BOARD_EBISU: 445 case BOARD_EBISU_4D: 446 ret = fdt_setprop_string(dt, 0, "compatible", 447 "renesas,ebisu"); 448 break; 449 case BOARD_DRAAK: 450 ret = fdt_setprop_string(dt, 0, "compatible", 451 "renesas,draak"); 452 break; 453 default: 454 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 455 panic(); 456 } 457 458 if (ret < 0) { 459 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 460 panic(); 461 } 462 463 reg = mmio_read_32(RCAR_PRR); 464 switch (reg & PRR_PRODUCT_MASK) { 465 case PRR_PRODUCT_H3: 466 ret = fdt_appendprop_string(dt, 0, "compatible", 467 "renesas,r8a7795"); 468 break; 469 case PRR_PRODUCT_M3: 470 ret = fdt_appendprop_string(dt, 0, "compatible", 471 "renesas,r8a7796"); 472 break; 473 case PRR_PRODUCT_M3N: 474 ret = fdt_appendprop_string(dt, 0, "compatible", 475 "renesas,r8a77965"); 476 break; 477 case PRR_PRODUCT_V3M: 478 ret = fdt_appendprop_string(dt, 0, "compatible", 479 "renesas,r8a77970"); 480 break; 481 case PRR_PRODUCT_E3: 482 ret = fdt_appendprop_string(dt, 0, "compatible", 483 "renesas,r8a77990"); 484 break; 485 case PRR_PRODUCT_D3: 486 ret = fdt_appendprop_string(dt, 0, "compatible", 487 "renesas,r8a77995"); 488 break; 489 default: 490 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 491 panic(); 492 } 493 494 if (ret < 0) { 495 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 496 panic(); 497 } 498 } 499 500 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 501 { 502 char nodename[32] = { 0 }; 503 uint64_t start, size; 504 uint64_t fdtsize; 505 int ret, node, chan; 506 507 for (chan = 0; chan < 4; chan++) { 508 start = dram_config[2 * chan]; 509 size = dram_config[2 * chan + 1]; 510 if (!size) 511 continue; 512 513 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 514 chan, start, start + size - 1, 515 (size >> 30) ? : size >> 20, 516 (size >> 30) ? "G" : "M"); 517 } 518 519 /* 520 * We add the DT nodes in reverse order here. The fdt_add_subnode() 521 * adds the DT node before the first existing DT node, so we have 522 * to add them in reverse order to get nodes sorted by address in 523 * the resulting DT. 524 */ 525 for (chan = 3; chan >= 0; chan--) { 526 start = dram_config[2 * chan]; 527 size = dram_config[2 * chan + 1]; 528 if (!size) 529 continue; 530 531 /* 532 * Channel 0 is mapped in 32bit space and the first 533 * 128 MiB are reserved 534 */ 535 if (chan == 0) { 536 start = 0x48000000; 537 size -= 0x8000000; 538 } 539 540 fdtsize = cpu_to_fdt64(size); 541 542 snprintf(nodename, sizeof(nodename), "memory@"); 543 unsigned_num_print(start, 16, nodename + strlen(nodename)); 544 node = ret = fdt_add_subnode(fdt, 0, nodename); 545 if (ret < 0) 546 goto err; 547 548 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 549 if (ret < 0) 550 goto err; 551 552 ret = fdt_setprop_u64(fdt, node, "reg", start); 553 if (ret < 0) 554 goto err; 555 556 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 557 sizeof(fdtsize)); 558 if (ret < 0) 559 goto err; 560 } 561 562 return; 563 err: 564 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 565 panic(); 566 } 567 568 static void bl2_advertise_dram_size(uint32_t product) 569 { 570 uint64_t dram_config[8] = { 571 [0] = 0x400000000ULL, 572 [2] = 0x500000000ULL, 573 [4] = 0x600000000ULL, 574 [6] = 0x700000000ULL, 575 }; 576 577 switch (product) { 578 case PRR_PRODUCT_H3: 579 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 580 /* 4GB(1GBx4) */ 581 dram_config[1] = 0x40000000ULL; 582 dram_config[3] = 0x40000000ULL; 583 dram_config[5] = 0x40000000ULL; 584 dram_config[7] = 0x40000000ULL; 585 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 586 (RCAR_DRAM_CHANNEL == 5) && \ 587 (RCAR_DRAM_SPLIT == 2) 588 /* 4GB(2GBx2 2ch split) */ 589 dram_config[1] = 0x80000000ULL; 590 dram_config[3] = 0x80000000ULL; 591 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 592 /* 8GB(2GBx4: default) */ 593 dram_config[1] = 0x80000000ULL; 594 dram_config[3] = 0x80000000ULL; 595 dram_config[5] = 0x80000000ULL; 596 dram_config[7] = 0x80000000ULL; 597 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 598 break; 599 600 case PRR_PRODUCT_M3: 601 #if (RCAR_GEN3_ULCB == 1) 602 /* 2GB(1GBx2 2ch split) */ 603 dram_config[1] = 0x40000000ULL; 604 dram_config[5] = 0x40000000ULL; 605 #else 606 /* 4GB(2GBx2 2ch split) */ 607 dram_config[1] = 0x80000000ULL; 608 dram_config[5] = 0x80000000ULL; 609 #endif 610 break; 611 612 case PRR_PRODUCT_M3N: 613 /* 2GB(1GBx2) */ 614 dram_config[1] = 0x80000000ULL; 615 break; 616 617 case PRR_PRODUCT_V3M: 618 /* 1GB(512MBx2) */ 619 dram_config[1] = 0x40000000ULL; 620 break; 621 622 case PRR_PRODUCT_E3: 623 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 624 /* 1GB(512MBx2) */ 625 dram_config[1] = 0x40000000ULL; 626 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 627 /* 2GB(512MBx4) */ 628 dram_config[1] = 0x80000000ULL; 629 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 630 /* 4GB(1GBx4) */ 631 dram_config[1] = 0x100000000ULL; 632 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 633 break; 634 635 case PRR_PRODUCT_D3: 636 /* 512MB */ 637 dram_config[1] = 0x20000000ULL; 638 break; 639 } 640 641 bl2_advertise_dram_entries(dram_config); 642 } 643 644 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 645 u_register_t arg3, u_register_t arg4) 646 { 647 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 648 uint32_t product, product_cut, major, minor; 649 int32_t ret; 650 const char *str; 651 const char *unknown = "unknown"; 652 const char *cpu_ca57 = "CA57"; 653 const char *cpu_ca53 = "CA53"; 654 const char *product_m3n = "M3N"; 655 const char *product_h3 = "H3"; 656 const char *product_m3 = "M3"; 657 const char *product_e3 = "E3"; 658 const char *product_d3 = "D3"; 659 const char *product_v3m = "V3M"; 660 const char *lcs_secure = "SE"; 661 const char *lcs_cm = "CM"; 662 const char *lcs_dm = "DM"; 663 const char *lcs_sd = "SD"; 664 const char *lcs_fa = "FA"; 665 const char *sscg_off = "PLL1 nonSSCG Clock select"; 666 const char *sscg_on = "PLL1 SSCG Clock select"; 667 const char *boot_hyper80 = "HyperFlash(80MHz)"; 668 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 669 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 670 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 671 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 672 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 673 const char *boot_hyper160 = "HyperFlash(150MHz)"; 674 #else 675 const char *boot_hyper160 = "HyperFlash(160MHz)"; 676 #endif 677 #if (RCAR_LOSSY_ENABLE == 1) 678 int fcnlnode; 679 #endif 680 681 bl2_init_generic_timer(); 682 683 reg = mmio_read_32(RCAR_MODEMR); 684 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 685 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 686 687 bl2_cpg_init(); 688 689 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 690 boot_cpu == MODEMR_BOOT_CPU_CA53) { 691 rcar_pfc_init(); 692 rcar_console_boot_init(); 693 } 694 695 plat_rcar_gic_driver_init(); 696 plat_rcar_gic_init(); 697 rcar_swdt_init(); 698 699 /* FIQ interrupts are taken to EL3 */ 700 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 701 702 write_daifclr(DAIF_FIQ_BIT); 703 704 reg = read_midr(); 705 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 706 switch (midr) { 707 case MIDR_CA57: 708 str = cpu_ca57; 709 break; 710 case MIDR_CA53: 711 str = cpu_ca53; 712 break; 713 default: 714 str = unknown; 715 break; 716 } 717 718 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 719 version_of_renesas); 720 721 reg = mmio_read_32(RCAR_PRR); 722 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 723 product = reg & PRR_PRODUCT_MASK; 724 725 switch (product) { 726 case PRR_PRODUCT_H3: 727 str = product_h3; 728 break; 729 case PRR_PRODUCT_M3: 730 str = product_m3; 731 break; 732 case PRR_PRODUCT_M3N: 733 str = product_m3n; 734 break; 735 case PRR_PRODUCT_V3M: 736 str = product_v3m; 737 break; 738 case PRR_PRODUCT_E3: 739 str = product_e3; 740 break; 741 case PRR_PRODUCT_D3: 742 str = product_d3; 743 break; 744 default: 745 str = unknown; 746 break; 747 } 748 749 if ((PRR_PRODUCT_M3 == product) && 750 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 751 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 752 /* M3 Ver.1.1 or Ver.1.2 */ 753 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 754 str); 755 } else { 756 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 757 str, 758 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 759 } 760 } else { 761 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 762 major = major + RCAR_MAJOR_OFFSET; 763 minor = reg & RCAR_MINOR_MASK; 764 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 765 } 766 767 if (product == PRR_PRODUCT_E3) { 768 reg = mmio_read_32(RCAR_MODEMR); 769 sscg = reg & RCAR_SSCG_MASK; 770 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 771 NOTICE("BL2: %s\n", str); 772 } 773 774 rcar_get_board_type(&type, &rev); 775 776 switch (type) { 777 case BOARD_SALVATOR_X: 778 case BOARD_KRIEK: 779 case BOARD_STARTER_KIT: 780 case BOARD_SALVATOR_XS: 781 case BOARD_EBISU: 782 case BOARD_STARTER_KIT_PRE: 783 case BOARD_EBISU_4D: 784 case BOARD_DRAAK: 785 case BOARD_EAGLE: 786 break; 787 default: 788 type = BOARD_UNKNOWN; 789 break; 790 } 791 792 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 793 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 794 else { 795 NOTICE("BL2: Board is %s Rev.%d.%d\n", 796 GET_BOARD_NAME(type), 797 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 798 } 799 800 #if RCAR_LSI != RCAR_AUTO 801 if (product != TARGET_PRODUCT) { 802 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 803 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 804 panic(); 805 } 806 #endif 807 rcar_avs_init(); 808 rcar_avs_setting(); 809 810 switch (boot_dev) { 811 case MODEMR_BOOT_DEV_HYPERFLASH160: 812 str = boot_hyper160; 813 break; 814 case MODEMR_BOOT_DEV_HYPERFLASH80: 815 str = boot_hyper80; 816 break; 817 case MODEMR_BOOT_DEV_QSPI_FLASH40: 818 str = boot_qspi40; 819 break; 820 case MODEMR_BOOT_DEV_QSPI_FLASH80: 821 str = boot_qspi80; 822 break; 823 case MODEMR_BOOT_DEV_EMMC_25X1: 824 #if RCAR_LSI == RCAR_D3 825 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 826 panic(); 827 #endif 828 str = boot_emmc25x1; 829 break; 830 case MODEMR_BOOT_DEV_EMMC_50X8: 831 #if RCAR_LSI == RCAR_D3 832 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 833 panic(); 834 #endif 835 str = boot_emmc50x8; 836 break; 837 default: 838 str = unknown; 839 break; 840 } 841 NOTICE("BL2: Boot device is %s\n", str); 842 843 rcar_avs_setting(); 844 reg = rcar_rom_get_lcs(&lcs); 845 if (reg) { 846 str = unknown; 847 goto lcm_state; 848 } 849 850 switch (lcs) { 851 case LCS_CM: 852 str = lcs_cm; 853 break; 854 case LCS_DM: 855 str = lcs_dm; 856 break; 857 case LCS_SD: 858 str = lcs_sd; 859 break; 860 case LCS_SE: 861 str = lcs_secure; 862 break; 863 case LCS_FA: 864 str = lcs_fa; 865 break; 866 default: 867 str = unknown; 868 break; 869 } 870 871 lcm_state: 872 NOTICE("BL2: LCM state is %s\n", str); 873 874 rcar_avs_end(); 875 is_ddr_backup_mode(); 876 877 bl2_tzram_layout.total_base = BL31_BASE; 878 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 879 880 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 881 boot_cpu == MODEMR_BOOT_CPU_CA53) { 882 ret = rcar_dram_init(); 883 if (ret) { 884 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 885 panic(); 886 } 887 rcar_qos_init(); 888 } 889 890 /* Set up FDT */ 891 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 892 if (ret) { 893 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 894 panic(); 895 } 896 897 /* Add platform compatible string */ 898 bl2_populate_compatible_string(fdt); 899 900 /* Print DRAM layout */ 901 bl2_advertise_dram_size(product); 902 903 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 904 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 905 if (rcar_emmc_init() != EMMC_SUCCESS) { 906 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 907 panic(); 908 } 909 rcar_emmc_memcard_power(EMMC_POWER_ON); 910 if (rcar_emmc_mount() != EMMC_SUCCESS) { 911 NOTICE("BL2: Failed to eMMC mount operation.\n"); 912 panic(); 913 } 914 } else { 915 rcar_rpc_init(); 916 rcar_dma_init(); 917 } 918 919 reg = mmio_read_32(RST_WDTRSTCR); 920 reg &= ~WDTRSTCR_RWDT_RSTMSK; 921 reg |= WDTRSTCR_PASSWORD; 922 mmio_write_32(RST_WDTRSTCR, reg); 923 924 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 925 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 926 927 reg = mmio_read_32(RCAR_PRR); 928 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 929 mmio_write_32(CPG_CA57DBGRCR, 930 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 931 932 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 933 mmio_write_32(CPG_CA53DBGRCR, 934 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 935 936 if (product_cut == PRR_PRODUCT_H3_CUT10) { 937 reg = mmio_read_32(CPG_PLL2CR); 938 reg &= ~((uint32_t) 1 << 5); 939 mmio_write_32(CPG_PLL2CR, reg); 940 941 reg = mmio_read_32(CPG_PLL4CR); 942 reg &= ~((uint32_t) 1 << 5); 943 mmio_write_32(CPG_PLL4CR, reg); 944 945 reg = mmio_read_32(CPG_PLL0CR); 946 reg &= ~((uint32_t) 1 << 12); 947 mmio_write_32(CPG_PLL0CR, reg); 948 } 949 #if (RCAR_LOSSY_ENABLE == 1) 950 NOTICE("BL2: Lossy Decomp areas\n"); 951 952 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 953 if (fcnlnode < 0) { 954 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 955 fcnlnode); 956 panic(); 957 } 958 959 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 960 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 961 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 962 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 963 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 964 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 965 #endif 966 967 fdt_pack(fdt); 968 NOTICE("BL2: FDT at %p\n", fdt); 969 970 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 971 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 972 rcar_io_emmc_setup(); 973 else 974 rcar_io_setup(); 975 } 976 977 void bl2_el3_plat_arch_setup(void) 978 { 979 #if RCAR_BL2_DCACHE == 1 980 NOTICE("BL2: D-Cache enable\n"); 981 rcar_configure_mmu_el3(BL2_BASE, 982 BL2_END - BL2_BASE, 983 BL2_RO_BASE, BL2_RO_LIMIT 984 #if USE_COHERENT_MEM 985 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 986 #endif 987 ); 988 #endif 989 } 990 991 void bl2_platform_setup(void) 992 { 993 994 } 995 996 static void bl2_init_generic_timer(void) 997 { 998 /* FIXME: V3M 16.666 MHz ? */ 999 #if RCAR_LSI == RCAR_D3 1000 uint32_t reg_cntfid = EXTAL_DRAAK; 1001 #elif RCAR_LSI == RCAR_E3 1002 uint32_t reg_cntfid = EXTAL_EBISU; 1003 #else /* RCAR_LSI == RCAR_E3 */ 1004 uint32_t reg; 1005 uint32_t reg_cntfid; 1006 uint32_t modemr; 1007 uint32_t modemr_pll; 1008 uint32_t board_type; 1009 uint32_t board_rev; 1010 uint32_t pll_table[] = { 1011 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1012 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1013 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1014 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1015 }; 1016 1017 modemr = mmio_read_32(RCAR_MODEMR); 1018 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1019 1020 /* Set frequency data in CNTFID0 */ 1021 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1022 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1023 switch (modemr_pll) { 1024 case MD14_MD13_TYPE_0: 1025 rcar_get_board_type(&board_type, &board_rev); 1026 if (BOARD_SALVATOR_XS == board_type) { 1027 reg_cntfid = EXTAL_SALVATOR_XS; 1028 } 1029 break; 1030 case MD14_MD13_TYPE_3: 1031 if (PRR_PRODUCT_H3_CUT10 == reg) { 1032 reg_cntfid = reg_cntfid >> 1U; 1033 } 1034 break; 1035 default: 1036 /* none */ 1037 break; 1038 } 1039 #endif /* RCAR_LSI == RCAR_E3 */ 1040 /* Update memory mapped and register based freqency */ 1041 write_cntfrq_el0((u_register_t )reg_cntfid); 1042 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1043 /* Enable counter */ 1044 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1045 (uint32_t)CNTCR_EN); 1046 } 1047