1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 44 45 #if USE_COHERENT_MEM 46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 48 #endif 49 50 extern void plat_rcar_gic_driver_init(void); 51 extern void plat_rcar_gic_init(void); 52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 53 extern void bl2_system_cpg_init(void); 54 extern void bl2_secure_setting(void); 55 extern void bl2_cpg_init(void); 56 extern void rcar_io_emmc_setup(void); 57 extern void rcar_io_setup(void); 58 extern void rcar_swdt_release(void); 59 extern void rcar_swdt_init(void); 60 extern void rcar_rpc_init(void); 61 extern void rcar_pfc_init(void); 62 extern void rcar_dma_init(void); 63 64 static void bl2_init_generic_timer(void); 65 66 /* R-Car Gen3 product check */ 67 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 68 #define TARGET_PRODUCT RCAR_PRODUCT_H3 69 #define TARGET_NAME "R-Car H3" 70 #elif RCAR_LSI == RCAR_M3 71 #define TARGET_PRODUCT RCAR_PRODUCT_M3 72 #define TARGET_NAME "R-Car M3" 73 #elif RCAR_LSI == RCAR_M3N 74 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 75 #define TARGET_NAME "R-Car M3N" 76 #elif RCAR_LSI == RCAR_E3 77 #define TARGET_PRODUCT RCAR_PRODUCT_E3 78 #define TARGET_NAME "R-Car E3" 79 #elif RCAR_LSI == RCAR_D3 80 #define TARGET_PRODUCT RCAR_PRODUCT_D3 81 #define TARGET_NAME "R-Car D3" 82 #elif RCAR_LSI == RCAR_AUTO 83 #define TARGET_NAME "R-Car H3/M3/M3N" 84 #endif 85 86 #if (RCAR_LSI == RCAR_E3) 87 #define GPIO_INDT (GPIO_INDT6) 88 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 89 #else 90 #define GPIO_INDT (GPIO_INDT1) 91 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 92 #endif 93 94 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 95 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 96 assert_bl31_params_do_not_fit_in_shared_memory); 97 98 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 99 100 /* FDT with DRAM configuration */ 101 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 102 static void *fdt = (void *)fdt_blob; 103 104 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 105 char *string) 106 { 107 /* Just need enough space to store 64 bit decimal integer */ 108 char num_buf[20]; 109 int i = 0; 110 unsigned int rem; 111 112 do { 113 rem = unum % radix; 114 if (rem < 0xa) 115 num_buf[i] = '0' + rem; 116 else 117 num_buf[i] = 'a' + (rem - 0xa); 118 i++; 119 unum /= radix; 120 } while (unum > 0U); 121 122 while (--i >= 0) 123 *string++ = num_buf[i]; 124 } 125 126 #if (RCAR_LOSSY_ENABLE == 1) 127 typedef struct bl2_lossy_info { 128 uint32_t magic; 129 uint32_t a0; 130 uint32_t b0; 131 } bl2_lossy_info_t; 132 133 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 134 uint64_t end_addr, uint32_t format, 135 uint32_t enable, int fcnlnode) 136 { 137 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 138 char nodename[40] = { 0 }; 139 int ret, node; 140 141 /* Ignore undefined addresses */ 142 if (start_addr == 0 && end_addr == 0) 143 return; 144 145 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 146 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 147 148 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 149 if (ret < 0) { 150 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 151 panic(); 152 } 153 154 ret = fdt_setprop_string(fdt, node, "compatible", 155 "renesas,lossy-decompression"); 156 if (ret < 0) { 157 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 158 panic(); 159 } 160 161 ret = fdt_appendprop_string(fdt, node, "compatible", 162 "shared-dma-pool"); 163 if (ret < 0) { 164 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 165 panic(); 166 } 167 168 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 169 if (ret < 0) { 170 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 171 panic(); 172 } 173 174 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 175 if (ret < 0) { 176 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 177 panic(); 178 } 179 180 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 181 if (ret < 0) { 182 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 183 panic(); 184 } 185 186 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 187 if (ret < 0) { 188 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 189 panic(); 190 } 191 } 192 193 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 194 uint64_t end_addr, uint32_t format, 195 uint32_t enable, int fcnlnode) 196 { 197 bl2_lossy_info_t info; 198 uint32_t reg; 199 200 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 201 202 reg = format | (start_addr >> 20); 203 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 204 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 205 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 206 207 info.magic = 0x12345678U; 208 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 209 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 210 211 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 212 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 213 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 214 215 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 216 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 217 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 218 } 219 #endif 220 221 void bl2_plat_flush_bl31_params(void) 222 { 223 uint32_t product_cut, product, cut; 224 uint32_t boot_dev, boot_cpu; 225 uint32_t lcs, reg, val; 226 227 reg = mmio_read_32(RCAR_MODEMR); 228 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 229 230 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 231 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 232 emmc_terminate(); 233 234 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 235 bl2_secure_setting(); 236 237 reg = mmio_read_32(RCAR_PRR); 238 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 239 product = reg & RCAR_PRODUCT_MASK; 240 cut = reg & RCAR_CUT_MASK; 241 242 if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut) 243 goto tlb; 244 245 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 246 goto tlb; 247 248 if (product == RCAR_PRODUCT_D3) 249 goto tlb; 250 251 /* Disable MFIS write protection */ 252 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 253 254 tlb: 255 reg = mmio_read_32(RCAR_MODEMR); 256 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 257 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 258 boot_cpu != MODEMR_BOOT_CPU_CA53) 259 goto mmu; 260 261 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 262 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 263 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 264 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 265 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 266 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 267 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 268 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 269 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 270 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 271 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 272 } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || 273 (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { 274 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 275 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 276 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 277 } 278 279 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 280 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 281 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 282 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 283 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 284 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 285 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 286 287 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 288 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 289 } 290 291 mmu: 292 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 293 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 294 295 val = rcar_rom_get_lcs(&lcs); 296 if (val) { 297 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 298 panic(); 299 } 300 301 if (lcs == LCS_SE) 302 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 303 304 rcar_swdt_release(); 305 bl2_system_cpg_init(); 306 307 #if RCAR_BL2_DCACHE == 1 308 /* Disable data cache (clean and invalidate) */ 309 disable_mmu_el3(); 310 #endif 311 } 312 313 static uint32_t is_ddr_backup_mode(void) 314 { 315 #if RCAR_SYSTEM_SUSPEND 316 static uint32_t reason = RCAR_COLD_BOOT; 317 static uint32_t once; 318 319 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 320 uint8_t data; 321 #endif 322 if (once) 323 return reason; 324 325 once = 1; 326 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 327 return reason; 328 329 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 330 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 331 ERROR("BL2: REG Keep10 READ ERROR.\n"); 332 panic(); 333 } 334 335 if (KEEP10_MAGIC != data) 336 reason = RCAR_WARM_BOOT; 337 #else 338 reason = RCAR_WARM_BOOT; 339 #endif 340 return reason; 341 #else 342 return RCAR_COLD_BOOT; 343 #endif 344 } 345 346 int bl2_plat_handle_pre_image_load(unsigned int image_id) 347 { 348 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 349 bl_mem_params_node_t *bl_mem_params; 350 351 if (image_id != BL31_IMAGE_ID) 352 return 0; 353 354 bl_mem_params = get_bl_mem_params_node(image_id); 355 356 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 357 goto cold_boot; 358 359 *boot_kind = RCAR_WARM_BOOT; 360 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 361 362 console_flush(); 363 bl2_plat_flush_bl31_params(); 364 365 /* will not return */ 366 bl2_enter_bl31(&bl_mem_params->ep_info); 367 368 cold_boot: 369 *boot_kind = RCAR_COLD_BOOT; 370 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 371 372 return 0; 373 } 374 375 int bl2_plat_handle_post_image_load(unsigned int image_id) 376 { 377 static bl2_to_bl31_params_mem_t *params; 378 bl_mem_params_node_t *bl_mem_params; 379 380 if (!params) { 381 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 382 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 383 } 384 385 bl_mem_params = get_bl_mem_params_node(image_id); 386 387 switch (image_id) { 388 case BL31_IMAGE_ID: 389 break; 390 case BL32_IMAGE_ID: 391 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 392 sizeof(entry_point_info_t)); 393 break; 394 case BL33_IMAGE_ID: 395 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 396 sizeof(entry_point_info_t)); 397 break; 398 } 399 400 return 0; 401 } 402 403 struct meminfo *bl2_plat_sec_mem_layout(void) 404 { 405 return &bl2_tzram_layout; 406 } 407 408 static void bl2_populate_compatible_string(void *fdt) 409 { 410 uint32_t board_type; 411 uint32_t board_rev; 412 uint32_t reg; 413 int ret; 414 415 /* Populate compatible string */ 416 rcar_get_board_type(&board_type, &board_rev); 417 switch (board_type) { 418 case BOARD_SALVATOR_X: 419 ret = fdt_setprop_string(fdt, 0, "compatible", 420 "renesas,salvator-x"); 421 break; 422 case BOARD_SALVATOR_XS: 423 ret = fdt_setprop_string(fdt, 0, "compatible", 424 "renesas,salvator-xs"); 425 break; 426 case BOARD_STARTER_KIT: 427 ret = fdt_setprop_string(fdt, 0, "compatible", 428 "renesas,m3ulcb"); 429 break; 430 case BOARD_STARTER_KIT_PRE: 431 ret = fdt_setprop_string(fdt, 0, "compatible", 432 "renesas,h3ulcb"); 433 break; 434 case BOARD_EBISU: 435 case BOARD_EBISU_4D: 436 ret = fdt_setprop_string(fdt, 0, "compatible", 437 "renesas,ebisu"); 438 break; 439 case BOARD_DRAAK: 440 ret = fdt_setprop_string(fdt, 0, "compatible", 441 "renesas,draak"); 442 break; 443 default: 444 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 445 panic(); 446 } 447 448 if (ret < 0) { 449 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 450 panic(); 451 } 452 453 reg = mmio_read_32(RCAR_PRR); 454 switch (reg & RCAR_PRODUCT_MASK) { 455 case RCAR_PRODUCT_H3: 456 ret = fdt_appendprop_string(fdt, 0, "compatible", 457 "renesas,r8a7795"); 458 break; 459 case RCAR_PRODUCT_M3: 460 ret = fdt_appendprop_string(fdt, 0, "compatible", 461 "renesas,r8a7796"); 462 break; 463 case RCAR_PRODUCT_M3N: 464 ret = fdt_appendprop_string(fdt, 0, "compatible", 465 "renesas,r8a77965"); 466 break; 467 case RCAR_PRODUCT_E3: 468 ret = fdt_appendprop_string(fdt, 0, "compatible", 469 "renesas,r8a77990"); 470 break; 471 case RCAR_PRODUCT_D3: 472 ret = fdt_appendprop_string(fdt, 0, "compatible", 473 "renesas,r8a77995"); 474 break; 475 default: 476 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 477 panic(); 478 } 479 480 if (ret < 0) { 481 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 482 panic(); 483 } 484 } 485 486 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 487 { 488 char nodename[32] = { 0 }; 489 uint64_t start, size; 490 uint64_t fdtsize; 491 int ret, node, chan; 492 493 for (chan = 0; chan < 4; chan++) { 494 start = dram_config[2 * chan]; 495 size = dram_config[2 * chan + 1]; 496 if (!size) 497 continue; 498 499 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 500 chan, start, start + size - 1, 501 (size >> 30) ? : size >> 20, 502 (size >> 30) ? "G" : "M"); 503 } 504 505 /* 506 * We add the DT nodes in reverse order here. The fdt_add_subnode() 507 * adds the DT node before the first existing DT node, so we have 508 * to add them in reverse order to get nodes sorted by address in 509 * the resulting DT. 510 */ 511 for (chan = 3; chan >= 0; chan--) { 512 start = dram_config[2 * chan]; 513 size = dram_config[2 * chan + 1]; 514 if (!size) 515 continue; 516 517 /* 518 * Channel 0 is mapped in 32bit space and the first 519 * 128 MiB are reserved 520 */ 521 if (chan == 0) { 522 start = 0x48000000; 523 size -= 0x8000000; 524 } 525 526 fdtsize = cpu_to_fdt64(size); 527 528 snprintf(nodename, sizeof(nodename), "memory@"); 529 unsigned_num_print(start, 16, nodename + strlen(nodename)); 530 node = ret = fdt_add_subnode(fdt, 0, nodename); 531 if (ret < 0) 532 goto err; 533 534 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 535 if (ret < 0) 536 goto err; 537 538 ret = fdt_setprop_u64(fdt, node, "reg", start); 539 if (ret < 0) 540 goto err; 541 542 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 543 sizeof(fdtsize)); 544 if (ret < 0) 545 goto err; 546 } 547 548 return; 549 err: 550 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 551 panic(); 552 } 553 554 static void bl2_advertise_dram_size(uint32_t product) 555 { 556 uint64_t dram_config[8] = { 557 [0] = 0x400000000ULL, 558 [2] = 0x500000000ULL, 559 [4] = 0x600000000ULL, 560 [6] = 0x700000000ULL, 561 }; 562 563 switch (product) { 564 case RCAR_PRODUCT_H3: 565 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 566 /* 4GB(1GBx4) */ 567 dram_config[1] = 0x40000000ULL; 568 dram_config[3] = 0x40000000ULL; 569 dram_config[5] = 0x40000000ULL; 570 dram_config[7] = 0x40000000ULL; 571 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 572 (RCAR_DRAM_CHANNEL == 5) && \ 573 (RCAR_DRAM_SPLIT == 2) 574 /* 4GB(2GBx2 2ch split) */ 575 dram_config[1] = 0x80000000ULL; 576 dram_config[3] = 0x80000000ULL; 577 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 578 /* 8GB(2GBx4: default) */ 579 dram_config[1] = 0x80000000ULL; 580 dram_config[3] = 0x80000000ULL; 581 dram_config[5] = 0x80000000ULL; 582 dram_config[7] = 0x80000000ULL; 583 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 584 break; 585 586 case RCAR_PRODUCT_M3: 587 #if (RCAR_GEN3_ULCB == 1) 588 /* 2GB(1GBx2 2ch split) */ 589 dram_config[1] = 0x40000000ULL; 590 dram_config[5] = 0x40000000ULL; 591 #else 592 /* 4GB(2GBx2 2ch split) */ 593 dram_config[1] = 0x80000000ULL; 594 dram_config[5] = 0x80000000ULL; 595 #endif 596 break; 597 598 case RCAR_PRODUCT_M3N: 599 /* 2GB(1GBx2) */ 600 dram_config[1] = 0x80000000ULL; 601 break; 602 603 case RCAR_PRODUCT_E3: 604 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 605 /* 1GB(512MBx2) */ 606 dram_config[1] = 0x40000000ULL; 607 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 608 /* 2GB(512MBx4) */ 609 dram_config[1] = 0x80000000ULL; 610 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 611 /* 4GB(1GBx4) */ 612 dram_config[1] = 0x100000000ULL; 613 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 614 break; 615 616 case RCAR_PRODUCT_D3: 617 /* 512MB */ 618 dram_config[1] = 0x20000000ULL; 619 break; 620 } 621 622 bl2_advertise_dram_entries(dram_config); 623 } 624 625 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 626 u_register_t arg3, u_register_t arg4) 627 { 628 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 629 uint32_t product, product_cut, major, minor; 630 int32_t ret; 631 const char *str; 632 const char *unknown = "unknown"; 633 const char *cpu_ca57 = "CA57"; 634 const char *cpu_ca53 = "CA53"; 635 const char *product_m3n = "M3N"; 636 const char *product_h3 = "H3"; 637 const char *product_m3 = "M3"; 638 const char *product_e3 = "E3"; 639 const char *product_d3 = "D3"; 640 const char *lcs_secure = "SE"; 641 const char *lcs_cm = "CM"; 642 const char *lcs_dm = "DM"; 643 const char *lcs_sd = "SD"; 644 const char *lcs_fa = "FA"; 645 const char *sscg_off = "PLL1 nonSSCG Clock select"; 646 const char *sscg_on = "PLL1 SSCG Clock select"; 647 const char *boot_hyper80 = "HyperFlash(80MHz)"; 648 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 649 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 650 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 651 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 652 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 653 const char *boot_hyper160 = "HyperFlash(150MHz)"; 654 #else 655 const char *boot_hyper160 = "HyperFlash(160MHz)"; 656 #endif 657 #if (RCAR_LOSSY_ENABLE == 1) 658 int fcnlnode; 659 #endif 660 661 bl2_init_generic_timer(); 662 663 reg = mmio_read_32(RCAR_MODEMR); 664 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 665 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 666 667 bl2_cpg_init(); 668 669 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 670 boot_cpu == MODEMR_BOOT_CPU_CA53) { 671 rcar_pfc_init(); 672 /* console configuration (platform specific) done in driver */ 673 console_init(0, 0, 0); 674 } 675 676 plat_rcar_gic_driver_init(); 677 plat_rcar_gic_init(); 678 rcar_swdt_init(); 679 680 /* FIQ interrupts are taken to EL3 */ 681 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 682 683 write_daifclr(DAIF_FIQ_BIT); 684 685 reg = read_midr(); 686 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 687 switch (midr) { 688 case MIDR_CA57: 689 str = cpu_ca57; 690 break; 691 case MIDR_CA53: 692 str = cpu_ca53; 693 break; 694 default: 695 str = unknown; 696 break; 697 } 698 699 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 700 version_of_renesas); 701 702 reg = mmio_read_32(RCAR_PRR); 703 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 704 product = reg & RCAR_PRODUCT_MASK; 705 706 switch (product) { 707 case RCAR_PRODUCT_H3: 708 str = product_h3; 709 break; 710 case RCAR_PRODUCT_M3: 711 str = product_m3; 712 break; 713 case RCAR_PRODUCT_M3N: 714 str = product_m3n; 715 break; 716 case RCAR_PRODUCT_E3: 717 str = product_e3; 718 break; 719 case RCAR_PRODUCT_D3: 720 str = product_d3; 721 break; 722 default: 723 str = unknown; 724 break; 725 } 726 727 if ((RCAR_PRODUCT_M3 == product) && 728 (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) { 729 if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) { 730 /* M3 Ver.1.1 or Ver.1.2 */ 731 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 732 str); 733 } else { 734 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 735 str, 736 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 737 } 738 } else { 739 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 740 major = major + RCAR_MAJOR_OFFSET; 741 minor = reg & RCAR_MINOR_MASK; 742 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 743 } 744 745 if (product == RCAR_PRODUCT_E3) { 746 reg = mmio_read_32(RCAR_MODEMR); 747 sscg = reg & RCAR_SSCG_MASK; 748 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 749 NOTICE("BL2: %s\n", str); 750 } 751 752 rcar_get_board_type(&type, &rev); 753 754 switch (type) { 755 case BOARD_SALVATOR_X: 756 case BOARD_KRIEK: 757 case BOARD_STARTER_KIT: 758 case BOARD_SALVATOR_XS: 759 case BOARD_EBISU: 760 case BOARD_STARTER_KIT_PRE: 761 case BOARD_EBISU_4D: 762 case BOARD_DRAAK: 763 break; 764 default: 765 type = BOARD_UNKNOWN; 766 break; 767 } 768 769 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 770 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 771 else { 772 NOTICE("BL2: Board is %s Rev.%d.%d\n", 773 GET_BOARD_NAME(type), 774 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 775 } 776 777 #if RCAR_LSI != RCAR_AUTO 778 if (product != TARGET_PRODUCT) { 779 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 780 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 781 panic(); 782 } 783 #endif 784 rcar_avs_init(); 785 rcar_avs_setting(); 786 787 switch (boot_dev) { 788 case MODEMR_BOOT_DEV_HYPERFLASH160: 789 str = boot_hyper160; 790 break; 791 case MODEMR_BOOT_DEV_HYPERFLASH80: 792 str = boot_hyper80; 793 break; 794 case MODEMR_BOOT_DEV_QSPI_FLASH40: 795 str = boot_qspi40; 796 break; 797 case MODEMR_BOOT_DEV_QSPI_FLASH80: 798 str = boot_qspi80; 799 break; 800 case MODEMR_BOOT_DEV_EMMC_25X1: 801 #if RCAR_LSI == RCAR_D3 802 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 803 panic(); 804 #endif 805 str = boot_emmc25x1; 806 break; 807 case MODEMR_BOOT_DEV_EMMC_50X8: 808 #if RCAR_LSI == RCAR_D3 809 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 810 panic(); 811 #endif 812 str = boot_emmc50x8; 813 break; 814 default: 815 str = unknown; 816 break; 817 } 818 NOTICE("BL2: Boot device is %s\n", str); 819 820 rcar_avs_setting(); 821 reg = rcar_rom_get_lcs(&lcs); 822 if (reg) { 823 str = unknown; 824 goto lcm_state; 825 } 826 827 switch (lcs) { 828 case LCS_CM: 829 str = lcs_cm; 830 break; 831 case LCS_DM: 832 str = lcs_dm; 833 break; 834 case LCS_SD: 835 str = lcs_sd; 836 break; 837 case LCS_SE: 838 str = lcs_secure; 839 break; 840 case LCS_FA: 841 str = lcs_fa; 842 break; 843 default: 844 str = unknown; 845 break; 846 } 847 848 lcm_state: 849 NOTICE("BL2: LCM state is %s\n", str); 850 851 rcar_avs_end(); 852 is_ddr_backup_mode(); 853 854 bl2_tzram_layout.total_base = BL31_BASE; 855 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 856 857 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 858 boot_cpu == MODEMR_BOOT_CPU_CA53) { 859 ret = rcar_dram_init(); 860 if (ret) { 861 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 862 panic(); 863 } 864 rcar_qos_init(); 865 } 866 867 /* Set up FDT */ 868 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 869 if (ret) { 870 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 871 panic(); 872 } 873 874 /* Add platform compatible string */ 875 bl2_populate_compatible_string(fdt); 876 877 /* Print DRAM layout */ 878 bl2_advertise_dram_size(product); 879 880 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 881 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 882 if (rcar_emmc_init() != EMMC_SUCCESS) { 883 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 884 panic(); 885 } 886 rcar_emmc_memcard_power(EMMC_POWER_ON); 887 if (rcar_emmc_mount() != EMMC_SUCCESS) { 888 NOTICE("BL2: Failed to eMMC mount operation.\n"); 889 panic(); 890 } 891 } else { 892 rcar_rpc_init(); 893 rcar_dma_init(); 894 } 895 896 reg = mmio_read_32(RST_WDTRSTCR); 897 reg &= ~WDTRSTCR_RWDT_RSTMSK; 898 reg |= WDTRSTCR_PASSWORD; 899 mmio_write_32(RST_WDTRSTCR, reg); 900 901 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 902 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 903 904 reg = mmio_read_32(RCAR_PRR); 905 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 906 mmio_write_32(CPG_CA57DBGRCR, 907 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 908 909 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 910 mmio_write_32(CPG_CA53DBGRCR, 911 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 912 913 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 914 reg = mmio_read_32(CPG_PLL2CR); 915 reg &= ~((uint32_t) 1 << 5); 916 mmio_write_32(CPG_PLL2CR, reg); 917 918 reg = mmio_read_32(CPG_PLL4CR); 919 reg &= ~((uint32_t) 1 << 5); 920 mmio_write_32(CPG_PLL4CR, reg); 921 922 reg = mmio_read_32(CPG_PLL0CR); 923 reg &= ~((uint32_t) 1 << 12); 924 mmio_write_32(CPG_PLL0CR, reg); 925 } 926 #if (RCAR_LOSSY_ENABLE == 1) 927 NOTICE("BL2: Lossy Decomp areas\n"); 928 929 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 930 if (fcnlnode < 0) { 931 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 932 fcnlnode); 933 panic(); 934 } 935 936 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 937 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 938 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 939 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 940 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 941 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 942 #endif 943 944 fdt_pack(fdt); 945 NOTICE("BL2: FDT at %p\n", fdt); 946 947 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 948 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 949 rcar_io_emmc_setup(); 950 else 951 rcar_io_setup(); 952 } 953 954 void bl2_el3_plat_arch_setup(void) 955 { 956 #if RCAR_BL2_DCACHE == 1 957 NOTICE("BL2: D-Cache enable\n"); 958 rcar_configure_mmu_el3(BL2_BASE, 959 BL2_END - BL2_BASE, 960 BL2_RO_BASE, BL2_RO_LIMIT 961 #if USE_COHERENT_MEM 962 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 963 #endif 964 ); 965 #endif 966 } 967 968 void bl2_platform_setup(void) 969 { 970 971 } 972 973 static void bl2_init_generic_timer(void) 974 { 975 #if RCAR_LSI == RCAR_D3 976 uint32_t reg_cntfid = EXTAL_DRAAK; 977 #elif RCAR_LSI == RCAR_E3 978 uint32_t reg_cntfid = EXTAL_EBISU; 979 #else /* RCAR_LSI == RCAR_E3 */ 980 uint32_t reg; 981 uint32_t reg_cntfid; 982 uint32_t modemr; 983 uint32_t modemr_pll; 984 uint32_t board_type; 985 uint32_t board_rev; 986 uint32_t pll_table[] = { 987 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 988 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 989 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 990 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 991 }; 992 993 modemr = mmio_read_32(RCAR_MODEMR); 994 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 995 996 /* Set frequency data in CNTFID0 */ 997 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 998 reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 999 switch (modemr_pll) { 1000 case MD14_MD13_TYPE_0: 1001 rcar_get_board_type(&board_type, &board_rev); 1002 if (BOARD_SALVATOR_XS == board_type) { 1003 reg_cntfid = EXTAL_SALVATOR_XS; 1004 } 1005 break; 1006 case MD14_MD13_TYPE_3: 1007 if (RCAR_PRODUCT_H3_CUT10 == reg) { 1008 reg_cntfid = reg_cntfid >> 1U; 1009 } 1010 break; 1011 default: 1012 /* none */ 1013 break; 1014 } 1015 #endif /* RCAR_LSI == RCAR_E3 */ 1016 /* Update memory mapped and register based freqency */ 1017 write_cntfrq_el0((u_register_t )reg_cntfid); 1018 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1019 /* Enable counter */ 1020 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1021 (uint32_t)CNTCR_EN); 1022 } 1023