1*a758c0b6SStephan Gerhold /* 2*a758c0b6SStephan Gerhold * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> 3*a758c0b6SStephan Gerhold * 4*a758c0b6SStephan Gerhold * SPDX-License-Identifier: BSD-3-Clause 5*a758c0b6SStephan Gerhold */ 6*a758c0b6SStephan Gerhold 7*a758c0b6SStephan Gerhold #include <arch_helpers.h> 8*a758c0b6SStephan Gerhold #include <drivers/delay_timer.h> 9*a758c0b6SStephan Gerhold #include <lib/mmio.h> 10*a758c0b6SStephan Gerhold 11*a758c0b6SStephan Gerhold #include <msm8916_mmap.h> 12*a758c0b6SStephan Gerhold #include "msm8916_pm.h" 13*a758c0b6SStephan Gerhold 14*a758c0b6SStephan Gerhold #define CPU_PWR_CTL 0x4 15*a758c0b6SStephan Gerhold #define APC_PWR_GATE_CTL 0x14 16*a758c0b6SStephan Gerhold 17*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CLAMP BIT_32(0) 18*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1) 19*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_L1_RST_DIS BIT_32(2) 20*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3) 21*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_RST BIT_32(4) 22*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_COREPOR_RST BIT_32(5) 23*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_GATE_CLK BIT_32(6) 24*a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7) 25*a758c0b6SStephan Gerhold 26*a758c0b6SStephan Gerhold #define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0) 27*a758c0b6SStephan Gerhold #define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24) 28*a758c0b6SStephan Gerhold 29*a758c0b6SStephan Gerhold /* Boot a secondary CPU core for the first time. */ 30*a758c0b6SStephan Gerhold void msm8916_cpu_boot(unsigned int core) 31*a758c0b6SStephan Gerhold { 32*a758c0b6SStephan Gerhold uintptr_t acs = APCS_ALIAS_ACS(core); 33*a758c0b6SStephan Gerhold uint32_t pwr_ctl; 34*a758c0b6SStephan Gerhold 35*a758c0b6SStephan Gerhold pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP | 36*a758c0b6SStephan Gerhold CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST; 37*a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 38*a758c0b6SStephan Gerhold dsb(); 39*a758c0b6SStephan Gerhold 40*a758c0b6SStephan Gerhold mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN | 41*a758c0b6SStephan Gerhold APC_PWR_GATE_CTL_GHDS_CNT(16)); 42*a758c0b6SStephan Gerhold dsb(); 43*a758c0b6SStephan Gerhold udelay(2); 44*a758c0b6SStephan Gerhold 45*a758c0b6SStephan Gerhold pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP; 46*a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 47*a758c0b6SStephan Gerhold dsb(); 48*a758c0b6SStephan Gerhold 49*a758c0b6SStephan Gerhold pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS; 50*a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 51*a758c0b6SStephan Gerhold dsb(); 52*a758c0b6SStephan Gerhold udelay(2); 53*a758c0b6SStephan Gerhold 54*a758c0b6SStephan Gerhold pwr_ctl &= ~CPU_PWR_CTL_CLAMP; 55*a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 56*a758c0b6SStephan Gerhold dsb(); 57*a758c0b6SStephan Gerhold udelay(2); 58*a758c0b6SStephan Gerhold 59*a758c0b6SStephan Gerhold pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST); 60*a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 61*a758c0b6SStephan Gerhold dsb(); 62*a758c0b6SStephan Gerhold 63*a758c0b6SStephan Gerhold pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP; 64*a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 65*a758c0b6SStephan Gerhold dsb(); 66*a758c0b6SStephan Gerhold } 67