1a758c0b6SStephan Gerhold /* 2*1d7ed58fSStephan Gerhold * Copyright (c) 2021-2022, Stephan Gerhold <stephan@gerhold.net> 3a758c0b6SStephan Gerhold * 4a758c0b6SStephan Gerhold * SPDX-License-Identifier: BSD-3-Clause 5a758c0b6SStephan Gerhold */ 6a758c0b6SStephan Gerhold 7a758c0b6SStephan Gerhold #include <arch_helpers.h> 8*1d7ed58fSStephan Gerhold #include <common/debug.h> 9a758c0b6SStephan Gerhold #include <drivers/delay_timer.h> 10a758c0b6SStephan Gerhold #include <lib/mmio.h> 11a758c0b6SStephan Gerhold 12a758c0b6SStephan Gerhold #include "msm8916_pm.h" 13a758c0b6SStephan Gerhold 14a758c0b6SStephan Gerhold #define CPU_PWR_CTL 0x4 15a758c0b6SStephan Gerhold #define APC_PWR_GATE_CTL 0x14 16a758c0b6SStephan Gerhold 17a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CLAMP BIT_32(0) 18a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1) 19a758c0b6SStephan Gerhold #define CPU_PWR_CTL_L1_RST_DIS BIT_32(2) 20a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3) 21a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_RST BIT_32(4) 22a758c0b6SStephan Gerhold #define CPU_PWR_CTL_COREPOR_RST BIT_32(5) 23a758c0b6SStephan Gerhold #define CPU_PWR_CTL_GATE_CLK BIT_32(6) 24a758c0b6SStephan Gerhold #define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7) 25a758c0b6SStephan Gerhold 26a758c0b6SStephan Gerhold #define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0) 27a758c0b6SStephan Gerhold #define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24) 28a758c0b6SStephan Gerhold 29a758c0b6SStephan Gerhold /* Boot a secondary CPU core for the first time. */ 30*1d7ed58fSStephan Gerhold void msm8916_cpu_boot(uintptr_t acs) 31a758c0b6SStephan Gerhold { 32a758c0b6SStephan Gerhold uint32_t pwr_ctl; 33a758c0b6SStephan Gerhold 34*1d7ed58fSStephan Gerhold VERBOSE("PSCI: Powering on CPU @ 0x%08lx\n", acs); 35*1d7ed58fSStephan Gerhold 36a758c0b6SStephan Gerhold pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP | 37a758c0b6SStephan Gerhold CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST; 38a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 39a758c0b6SStephan Gerhold dsb(); 40a758c0b6SStephan Gerhold 41a758c0b6SStephan Gerhold mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN | 42a758c0b6SStephan Gerhold APC_PWR_GATE_CTL_GHDS_CNT(16)); 43a758c0b6SStephan Gerhold dsb(); 44a758c0b6SStephan Gerhold udelay(2); 45a758c0b6SStephan Gerhold 46a758c0b6SStephan Gerhold pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP; 47a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 48a758c0b6SStephan Gerhold dsb(); 49a758c0b6SStephan Gerhold 50a758c0b6SStephan Gerhold pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS; 51a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 52a758c0b6SStephan Gerhold dsb(); 53a758c0b6SStephan Gerhold udelay(2); 54a758c0b6SStephan Gerhold 55a758c0b6SStephan Gerhold pwr_ctl &= ~CPU_PWR_CTL_CLAMP; 56a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 57a758c0b6SStephan Gerhold dsb(); 58a758c0b6SStephan Gerhold udelay(2); 59a758c0b6SStephan Gerhold 60a758c0b6SStephan Gerhold pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST); 61a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 62a758c0b6SStephan Gerhold dsb(); 63a758c0b6SStephan Gerhold 64a758c0b6SStephan Gerhold pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP; 65a758c0b6SStephan Gerhold mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl); 66a758c0b6SStephan Gerhold dsb(); 67a758c0b6SStephan Gerhold } 68