Merge changes from topic "msm8916-plats" into integration

* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms

Merge changes from topic "msm8916-plats" into integration

* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms
feat(msm8916): add port for MSM8939
feat(msm8916): power on L2 caches for secondary clusters
feat(msm8916): initialize CCI-400 for multiple clusters
refactor(msm8916): handle multiple CPU clusters
feat(msm8916): add port for MSM8909
feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+
style(msm8916): add missing braces to while statements

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feat(msm8916): initialize CCI-400 for multiple clusters

The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to

feat(msm8916): initialize CCI-400 for multiple clusters

The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to initialize it with the existing driver.

No functional change for platforms with a single cluster. The CCI
related code is discarded entirely in this case.

Change-Id: I041d60222d8d2aeca53b392934c87280c66b0db0
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes from topic "msm8916-spmin" into integration

* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port f

Merge changes from topic "msm8916-spmin" into integration

* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port for AArch32
refactor(msm8916): detect cold boot in plat_get_my_entrypoint
feat(msm8916): add Test Secure Payload (TSP) port
build(msm8916): place bl32 directly after bl31
refactor(msm8916): separate common platform setup code

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refactor(msm8916): separate common platform setup code

In preparation of adding BL32 support for the msm8916 platform
(AArch32/SP_MIN and TSP), separate the common platform setup code into
shared ms

refactor(msm8916): separate common platform setup code

In preparation of adding BL32 support for the msm8916 platform
(AArch32/SP_MIN and TSP), separate the common platform setup code into
shared msm8916_setup.c and msm8916_config.c files which can be called
from both BL31 and BL32.

msm8916_setup.c contains the relevant shared code for BL31/SP_MIN/TSP,
while msm8916_config.c is cold boot configuration code that is only
relevant for BL31 and SP_MIN (but not TSP).

No functional change.

Change-Id: I055522d5ad8c03dfb8e09236dc47dd383a480e95
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration

* changes:
fix(msm8916): add timeout for crash console TX flush
style(msm8916): use size macros
feat(msm89

Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration

* changes:
fix(msm8916): add timeout for crash console TX flush
style(msm8916): use size macros
feat(msm8916): expose more timer frames
fix(msm8916): drop unneeded initialization of CNTACR
build(msm8916): disable unneeded workarounds
fix(msm8916): flush dcache after writing msm8916_entry_point
fix(msm8916): print \r before \n on UART console

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feat(msm8916): expose more timer frames

The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is curr

feat(msm8916): expose more timer frames

The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is currently only designed to be used as minimal PSCI
implementation, without secure world that could make use of the other
timer frames. Let's make all of them available to the normal world.

If needed this could still be changed later by reserving some timer
frames conditionally to a specific SPD being enabled in the build.

Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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fix(msm8916): drop unneeded initialization of CNTACR

Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initia

fix(msm8916): drop unneeded initialization of CNTACR

Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initialization in BL31 so drop it before anything starts to rely on it.

Related issue: https://github.com/ARM-software/tf-issues/issues/170

Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes from topic "msm8916" into integration

* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding G

Merge changes from topic "msm8916" into integration

* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding GICD_PIDR2_GICV2 address
feat(msm8916): initial platform port
docs(msm8916): new port for Qualcomm Snapdragon 410

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feat(msm8916): allow booting secondary CPU cores

Add support for the PSCI CPU_ON call to allow booting secondary CPU
cores. On cold boot they need to be booted with a special register
sequence. Also

feat(msm8916): allow booting secondary CPU cores

Add support for the PSCI CPU_ON call to allow booting secondary CPU
cores. On cold boot they need to be booted with a special register
sequence. Also, the "boot remapper" needs to be configured to point to
the BL31_BASE, so the CPUs actually start executing BL31 after reset.

Change-Id: I406c508070ccb046bfdefd51554f12e1db671fd4
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): setup hardware for non-secure world

Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secu

feat(msm8916): setup hardware for non-secure world

Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secure world. Add more platform initialization to:

- Initialize the GICv2 and mark secure interrupts.
Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2
register address in platform_def.h to avoid a failing assert()
because of a (hardware) mistake in Qualcomm's GICv2 implementation.

- Make a timer frame available to the non-secure world.
The "Qualcomm Timer" (QTMR) implements the ARM generic timer
specification, so the standard defines (CNTACR_BASE etc)
can be used.

- Make parts of the "APCS" register region available to the
non-secure world, e.g. for CPU frequency control implemented
in Linux.

- Initialize a platform-specific register to route all SMMU context
bank interrupts to the non-secure interrupt pin, since all control
of the SMMUs is left up to the non-secure world for now.

Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): initial platform port

Introduce the bare mimimum base of the msm8916 BL31 port. This is
pretty much just a standard platform "skeleton" with CPU/memory
initialization and an UART driv

feat(msm8916): initial platform port

Introduce the bare mimimum base of the msm8916 BL31 port. This is
pretty much just a standard platform "skeleton" with CPU/memory
initialization and an UART driver. This allows booting into
e.g. U-Boot with working UART output.

Note that the plat/qti/msm8916 port is completely separate and does not
make use of anything in plat/qti/common at the moment. The main reason
for that is that plat/qti/common is heavily focused around having a
binary "qtiseclib" component, while the MSM8916 port is fully
open-source (and therefore somewhat limited to publicly documented
functionality).

In the future it might be possible to re-use some of the open-source
parts in plat/qti/common (e.g. spmi_arb.c or pm_ps_hold.c) but it's
not strictly required for the basic functionality supported so far.

Change-Id: I7b4375df0f947b3bd1e55b0b52b21edb6e6d175b
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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