1dddba19aSStephan Gerhold /* 2dddba19aSStephan Gerhold * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> 3dddba19aSStephan Gerhold * 4dddba19aSStephan Gerhold * SPDX-License-Identifier: BSD-3-Clause 5dddba19aSStephan Gerhold */ 6dddba19aSStephan Gerhold #ifndef PLATFORM_DEF_H 7dddba19aSStephan Gerhold #define PLATFORM_DEF_H 8dddba19aSStephan Gerhold 9dddba19aSStephan Gerhold #include <plat/common/common_def.h> 10dddba19aSStephan Gerhold 11dddba19aSStephan Gerhold /* 12dddba19aSStephan Gerhold * There is at least 1 MiB available for BL31. However, at the moment the 13dddba19aSStephan Gerhold * "msm8916_entry_point" variable in the data section is read through the 14dddba19aSStephan Gerhold * 64 KiB region of the "boot remapper" after reset. For simplicity, limit 15dddba19aSStephan Gerhold * the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and 16dddba19aSStephan Gerhold * the overall limit to 128 KiB. This could be increased if needed by placing 17dddba19aSStephan Gerhold * the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31. 18dddba19aSStephan Gerhold */ 19a27e3f76SStephan Gerhold #define BL31_LIMIT (BL31_BASE + SZ_128K) 20a27e3f76SStephan Gerhold #define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K) 21*4181ec8cSStephan Gerhold #define BL32_LIMIT (BL32_BASE + SZ_128K) 22dddba19aSStephan Gerhold 23dddba19aSStephan Gerhold #define CACHE_WRITEBACK_GRANULE U(64) 24a27e3f76SStephan Gerhold #define PLATFORM_STACK_SIZE SZ_4K 25dddba19aSStephan Gerhold 26dddba19aSStephan Gerhold /* CPU topology: single cluster with 4 cores */ 27dddba19aSStephan Gerhold #define PLATFORM_CLUSTER_COUNT U(1) 28dddba19aSStephan Gerhold #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 29dddba19aSStephan Gerhold #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 30dddba19aSStephan Gerhold PLATFORM_MAX_CPUS_PER_CLUSTER) 31dddba19aSStephan Gerhold 32dddba19aSStephan Gerhold /* Power management */ 33dddba19aSStephan Gerhold #define PLATFORM_SYSTEM_COUNT U(1) 34dddba19aSStephan Gerhold #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 35dddba19aSStephan Gerhold PLATFORM_CLUSTER_COUNT + \ 36dddba19aSStephan Gerhold PLATFORM_CORE_COUNT) 37dddba19aSStephan Gerhold #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 38dddba19aSStephan Gerhold #define PLAT_MAX_RET_STATE U(2) 39dddba19aSStephan Gerhold #define PLAT_MAX_OFF_STATE U(3) 40dddba19aSStephan Gerhold 41dddba19aSStephan Gerhold /* Translation tables */ 42dddba19aSStephan Gerhold #define MAX_MMAP_REGIONS 8 43dddba19aSStephan Gerhold #define MAX_XLAT_TABLES 4 44dddba19aSStephan Gerhold 45dddba19aSStephan Gerhold #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 46dddba19aSStephan Gerhold #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 47dddba19aSStephan Gerhold 48dddba19aSStephan Gerhold /* Timer frequency */ 49dddba19aSStephan Gerhold #define PLAT_SYSCNT_FREQ 19200000 50dddba19aSStephan Gerhold 51af644731SStephan Gerhold /* 52af644731SStephan Gerhold * The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7 53af644731SStephan Gerhold * erroneously swapped for some reason. PIDR2 is actually at 0xFD8. 54af644731SStephan Gerhold * Override the address in <drivers/arm/gicv2.h> to avoid a failing assert(). 55af644731SStephan Gerhold */ 56af644731SStephan Gerhold #define GICD_PIDR2_GICV2 U(0xFD8) 57af644731SStephan Gerhold 58dddba19aSStephan Gerhold #endif /* PLATFORM_DEF_H */ 59