1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2019-2020, Linaro Limited and Contributors. 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <tbbr_img_def.h> 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define PLATFORM_STACK_SIZE 0x1000 18 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 20 #define PLATFORM_CLUSTER_COUNT U(2) 21 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 22 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 23 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 24 PLATFORM_CLUSTER1_CORE_COUNT) 25 26 #define QEMU_PRIMARY_CPU U(0) 27 28 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 29 PLATFORM_CORE_COUNT) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 31 32 #define PLAT_MAX_RET_STATE 1 33 #define PLAT_MAX_OFF_STATE 2 34 35 /* Local power state for power domains in Run state. */ 36 #define PLAT_LOCAL_STATE_RUN 0 37 /* Local power state for retention. Valid only for CPU power domains */ 38 #define PLAT_LOCAL_STATE_RET 1 39 /* 40 * Local power state for OFF/power-down. Valid for CPU and cluster power 41 * domains. 42 */ 43 #define PLAT_LOCAL_STATE_OFF 2 44 45 /* 46 * Macros used to parse state information from State-ID if it is using the 47 * recommended encoding for State-ID. 48 */ 49 #define PLAT_LOCAL_PSTATE_WIDTH 4 50 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 51 52 /* 53 * Some data must be aligned on the biggest cache line size in the platform. 54 * This is known only to the platform as it might have a combination of 55 * integrated and external caches. 56 */ 57 #define CACHE_WRITEBACK_SHIFT 6 58 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 59 60 /* 61 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 62 * and secure DRAM. 63 */ 64 #define SEC_ROM_BASE 0x00000000 65 #define SEC_ROM_SIZE 0x00020000 66 67 #define NS_DRAM0_BASE 0x10000000000ULL 68 #define NS_DRAM0_SIZE 0x00020000000 69 70 #define SEC_SRAM_BASE 0x20000000 71 #define SEC_SRAM_SIZE 0x20000000 72 73 /* 74 * RAD just placeholders, need to be chosen after finalizing mem map 75 */ 76 #define SEC_DRAM_BASE 0x1000 77 #define SEC_DRAM_SIZE 0x1000 78 79 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 80 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 81 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 82 83 /* 84 * ARM-TF lives in SRAM, partition it here 85 */ 86 87 #define SHARED_RAM_BASE SEC_SRAM_BASE 88 #define SHARED_RAM_SIZE 0x00001000 89 90 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 91 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 92 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 93 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 94 PLAT_QEMU_HOLD_ENTRY_SIZE) 95 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 96 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 97 #define PLAT_QEMU_HOLD_STATE_WAIT 0 98 #define PLAT_QEMU_HOLD_STATE_GO 1 99 100 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 101 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 102 103 /* 104 * BL1 specific defines. 105 * 106 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 107 * addresses. 108 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 109 * the current BL1 RW debug size plus a little space for growth. 110 */ 111 #define BL1_SIZE 0x12000 112 #define BL1_RO_BASE SEC_ROM_BASE 113 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 114 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) 115 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 116 117 /* 118 * BL2 specific defines. 119 * 120 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 121 * size plus a little space for growth. 122 */ 123 #define BL2_SIZE 0x1D000 124 #define BL2_BASE (BL31_BASE - BL2_SIZE) 125 #define BL2_LIMIT BL31_BASE 126 127 /* 128 * BL3-1 specific defines. 129 * 130 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 131 * current BL3-1 debug size plus a little space for growth. 132 */ 133 #define BL31_SIZE 0x50000 134 #define BL31_BASE (BL31_LIMIT - BL31_SIZE) 135 #define BL31_LIMIT (BL1_RW_BASE) 136 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 137 138 139 /* 140 * BL3-2 specific defines. 141 * 142 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 143 */ 144 #define BL32_SRAM_BASE BL_RAM_BASE 145 #define BL32_SRAM_LIMIT BL2_BASE 146 147 #define BL32_MEM_BASE BL_RAM_BASE 148 #define BL32_MEM_SIZE (BL_RAM_SIZE - BL1_SIZE - \ 149 BL2_SIZE - BL31_SIZE) 150 #define BL32_BASE BL32_SRAM_BASE 151 #define BL32_LIMIT BL32_SRAM_LIMIT 152 153 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 154 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 155 156 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) 157 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) 158 #if SPM_MM 159 #define MAX_MMAP_REGIONS 12 160 #define MAX_XLAT_TABLES 11 161 #else 162 #define MAX_MMAP_REGIONS 11 163 #define MAX_XLAT_TABLES 10 164 #endif 165 #define MAX_IO_DEVICES 3 166 #define MAX_IO_HANDLES 4 167 168 #if SPM_MM && defined(IMAGE_BL31) 169 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 170 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20 171 #endif 172 173 /* 174 * PL011 related constants 175 */ 176 #define UART0_BASE 0x60000000 177 #define UART1_BASE 0x60030000 178 #define UART0_CLK_IN_HZ 1 179 #define UART1_CLK_IN_HZ 1 180 181 /* Secure UART */ 182 #define UART2_BASE 0x60040000 183 #define UART2_CLK_IN_HZ 1 184 185 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 186 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 187 188 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 189 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 190 191 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 192 193 #define QEMU_FLASH0_BASE 0x00000000 194 #define QEMU_FLASH0_SIZE 0x10000000 195 #define QEMU_FLASH1_BASE 0x10000000 196 #define QEMU_FLASH1_SIZE 0x10000000 197 198 #define PLAT_QEMU_FIP_BASE 0x00008000 199 #define PLAT_QEMU_FIP_MAX_SIZE 0x00400000 200 201 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ 202 #define DEVICE0_BASE 0x40000000 203 #define DEVICE0_SIZE 0x04080000 204 /* This is map from NORMAL_UART up to SECURE_UART_MM */ 205 #define DEVICE1_BASE 0x60000000 206 #define DEVICE1_SIZE 0x00041000 207 208 /* 209 * GIC related constants 210 * We use GICv3 where CPU Interface registers are not memory mapped 211 */ 212 #define GICD_BASE 0x40060000 213 #define GICR_BASE 0x40080000 214 #define GICC_BASE 0x0 215 216 #define QEMU_IRQ_SEC_SGI_0 8 217 #define QEMU_IRQ_SEC_SGI_1 9 218 #define QEMU_IRQ_SEC_SGI_2 10 219 #define QEMU_IRQ_SEC_SGI_3 11 220 #define QEMU_IRQ_SEC_SGI_4 12 221 #define QEMU_IRQ_SEC_SGI_5 13 222 #define QEMU_IRQ_SEC_SGI_6 14 223 #define QEMU_IRQ_SEC_SGI_7 15 224 225 /****************************************************************************** 226 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 227 * interrupts. 228 *****************************************************************************/ 229 #define PLATFORM_G1S_PROPS(grp) \ 230 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 231 grp, GIC_INTR_CFG_EDGE), \ 232 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 233 grp, GIC_INTR_CFG_EDGE), \ 234 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 235 grp, GIC_INTR_CFG_EDGE), \ 236 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 237 grp, GIC_INTR_CFG_EDGE), \ 238 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 239 grp, GIC_INTR_CFG_EDGE), \ 240 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 241 grp, GIC_INTR_CFG_EDGE), \ 242 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 243 grp, GIC_INTR_CFG_EDGE), \ 244 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 245 grp, GIC_INTR_CFG_EDGE) 246 247 #define PLATFORM_G0_PROPS(grp) 248 249 /* 250 * DT related constants 251 */ 252 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 253 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 254 255 /* 256 * System counter 257 */ 258 #define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) 259 260 #if SPM_MM 261 #define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE 262 #define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000) 263 264 #ifdef IMAGE_BL2 265 /* In BL2 all memory allocated to the SPM Payload image is marked as RW. */ 266 # define QEMU_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 267 PLAT_QEMU_SP_IMAGE_BASE, \ 268 PLAT_QEMU_SP_IMAGE_SIZE, \ 269 MT_MEMORY | MT_RW | \ 270 MT_SECURE) 271 #elif IMAGE_BL31 272 /* All SPM Payload memory is marked as code in S-EL0 */ 273 # define QEMU_SP_IMAGE_MMAP MAP_REGION2(PLAT_QEMU_SP_IMAGE_BASE, \ 274 PLAT_QEMU_SP_IMAGE_BASE, \ 275 PLAT_QEMU_SP_IMAGE_SIZE, \ 276 MT_CODE | MT_SECURE | \ 277 MT_USER, \ 278 PAGE_SIZE) 279 #endif 280 281 /* 282 * EL3 -> S-EL0 secure shared memory 283 */ 284 #define PLAT_SPM_BUF_PCPU_SIZE ULL(0x10000) 285 #define PLAT_SPM_BUF_SIZE (PLATFORM_CORE_COUNT * \ 286 PLAT_SPM_BUF_PCPU_SIZE) 287 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - PLAT_SPM_BUF_SIZE) 288 289 #define QEMU_SPM_BUF_EL3_MMAP MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, \ 290 PLAT_SPM_BUF_SIZE, \ 291 MT_RW_DATA | MT_SECURE) 292 293 #define QEMU_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 294 PLAT_SPM_BUF_BASE, \ 295 PLAT_SPM_BUF_SIZE, \ 296 MT_RO_DATA | MT_SECURE | \ 297 MT_USER, \ 298 PAGE_SIZE) 299 300 /* 301 * Shared memory between Normal world and S-EL0 for 302 * passing data during service requests. It will be marked as RW and NS. 303 */ 304 #define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \ 305 PLAT_QEMU_DT_MAX_SIZE) 306 #define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 307 #define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 308 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 309 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 310 PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, \ 311 MT_RW_DATA | MT_NS | \ 312 MT_USER, \ 313 PAGE_SIZE) 314 315 #define PLAT_SP_IMAGE_NS_BUF_BASE PLAT_QEMU_SP_IMAGE_NS_BUF_BASE 316 #define PLAT_SP_IMAGE_NS_BUF_SIZE PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE 317 318 #define PLAT_QEMU_SP_IMAGE_HEAP_BASE (PLAT_QEMU_SP_IMAGE_BASE + \ 319 PLAT_QEMU_SP_IMAGE_SIZE) 320 #define PLAT_QEMU_SP_IMAGE_HEAP_SIZE ULL(0x800000) 321 322 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_QEMU_SP_IMAGE_HEAP_BASE + \ 323 PLAT_QEMU_SP_IMAGE_HEAP_SIZE) 324 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 325 #define QEMU_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 326 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 327 328 #define QEMU_SP_IMAGE_RW_MMAP MAP_REGION2( \ 329 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 330 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 331 (QEMU_SP_IMAGE_STACK_TOTAL_SIZE + \ 332 PLAT_QEMU_SP_IMAGE_HEAP_SIZE), \ 333 MT_RW_DATA | MT_SECURE | \ 334 MT_USER, \ 335 PAGE_SIZE) 336 337 /* Total number of memory regions with distinct properties */ 338 #define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6 339 340 /* 341 * Name of the section to put the translation tables used by the S-EL1/S-EL0 342 * context of a Secure Partition. 343 */ 344 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME "qemu_sp_xlat_table" 345 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "qemu_sp_xlat_table" 346 347 /* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/ 348 #define PLAT_SPM_COOKIE_0 ULL(0) 349 #define PLAT_SPM_COOKIE_1 ULL(0) 350 #endif 351 352 #define QEMU_PRI_BITS 2 353 #define PLAT_SP_PRI 0x20 354 355 #endif /* PLATFORM_DEF_H */ 356