1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2019-2020, Linaro Limited and Contributors. 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <tbbr_img_def.h> 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 #define PLATFORM_STACK_SIZE 0x1000 18 19 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 20 /* 21 * Define the number of cores per cluster used in calculating core position. 22 * The cluster number is shifted by this value and added to the core ID, 23 * so its value represents log2(cores/cluster). 24 * Default is 2**(3) = 8 cores per cluster. 25 */ 26 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(3) 27 #define PLATFORM_CLUSTER_COUNT U(64) 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_MAX_CPUS_PER_CLUSTER) 30 #define QEMU_PRIMARY_CPU U(0) 31 32 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 33 PLATFORM_CORE_COUNT) 34 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 35 36 #define PLAT_MAX_RET_STATE 1 37 #define PLAT_MAX_OFF_STATE 2 38 39 /* Local power state for power domains in Run state. */ 40 #define PLAT_LOCAL_STATE_RUN 0 41 /* Local power state for retention. Valid only for CPU power domains */ 42 #define PLAT_LOCAL_STATE_RET 1 43 /* 44 * Local power state for OFF/power-down. Valid for CPU and cluster power 45 * domains. 46 */ 47 #define PLAT_LOCAL_STATE_OFF 2 48 49 /* 50 * Macros used to parse state information from State-ID if it is using the 51 * recommended encoding for State-ID. 52 */ 53 #define PLAT_LOCAL_PSTATE_WIDTH 4 54 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 55 56 /* 57 * Some data must be aligned on the biggest cache line size in the platform. 58 * This is known only to the platform as it might have a combination of 59 * integrated and external caches. 60 */ 61 #define CACHE_WRITEBACK_SHIFT 6 62 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 63 64 /* 65 * Define the max number of memory nodes. 66 */ 67 #define PLAT_MAX_MEM_NODES 128 68 69 /* Where QEMU starts the NS RAM */ 70 #define PLAT_QEMU_DRAM0_BASE 0x10000000000ULL 71 72 /* 73 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 74 * and secure DRAM. 75 */ 76 #define SEC_ROM_BASE 0x00000000 77 #define SEC_ROM_SIZE 0x00020000 78 79 /* 80 * When the RME extension is enabled, the base of the NS RAM is shifted after 81 * RMM. 82 */ 83 #define NS_DRAM0_BASE (PLAT_QEMU_DRAM0_BASE + \ 84 NS_DRAM0_BASE_OFFSET) 85 #define NS_DRAM0_SIZE 0x00020000000 86 87 #define SEC_SRAM_BASE 0x20000000 88 #define SEC_SRAM_SIZE 0x20000000 89 90 /* 91 * RAD just placeholders, need to be chosen after finalizing mem map 92 */ 93 #define SEC_DRAM_BASE 0x1000 94 #define SEC_DRAM_SIZE 0x1000 95 96 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 97 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 98 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 99 100 /* 101 * ARM-TF lives in SRAM, partition it here 102 */ 103 104 #define SHARED_RAM_BASE SEC_SRAM_BASE 105 #define SHARED_RAM_SIZE 0x00002000 106 107 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 108 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 109 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 110 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 111 PLAT_QEMU_HOLD_ENTRY_SIZE) 112 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 113 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 114 #define PLAT_QEMU_HOLD_STATE_WAIT 0 115 #define PLAT_QEMU_HOLD_STATE_GO 1 116 117 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 118 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 119 120 /* 121 * BL1 specific defines. 122 * 123 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 124 * addresses. 125 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 126 * the current BL1 RW debug size plus a little space for growth. 127 */ 128 #define BL1_SIZE 0x12000 129 #define BL1_RO_BASE SEC_ROM_BASE 130 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 131 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) 132 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - \ 133 RME_GPT_DRAM_SIZE) 134 135 /* 136 * BL2 specific defines. 137 * 138 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 139 * size plus a little space for growth. 140 */ 141 #define BL2_SIZE 0x1D000 142 #define BL2_BASE (BL31_BASE - BL2_SIZE) 143 #define BL2_LIMIT BL31_BASE 144 145 /* 146 * BL3-1 specific defines. 147 * 148 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 149 * current BL3-1 debug size plus a little space for growth. 150 */ 151 #define BL31_SIZE 0x400000 152 #define BL31_BASE (BL31_LIMIT - BL31_SIZE) 153 #define BL31_LIMIT (BL1_RW_BASE) 154 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 155 156 157 /* 158 * BL3-2 specific defines. 159 * 160 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 161 */ 162 #define BL32_SRAM_BASE BL_RAM_BASE 163 #define BL32_SRAM_LIMIT BL2_BASE 164 165 #define BL32_MEM_BASE BL_RAM_BASE 166 #define BL32_MEM_SIZE (BL_RAM_SIZE - RME_GPT_DRAM_SIZE - \ 167 BL1_SIZE - BL2_SIZE - BL31_SIZE) 168 #define BL32_BASE BL32_SRAM_BASE 169 #define BL32_LIMIT BL32_SRAM_LIMIT 170 171 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 172 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 173 174 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) 175 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) 176 #if SPM_MM 177 #define MAX_MMAP_REGIONS 12 178 #define MAX_XLAT_TABLES 12 179 #elif ENABLE_RME 180 #define MAX_MMAP_REGIONS 14 181 #define MAX_XLAT_TABLES 14 182 #else 183 #define MAX_MMAP_REGIONS 11 184 #define MAX_XLAT_TABLES 11 185 #endif 186 #define MAX_IO_DEVICES 3 187 #define MAX_IO_HANDLES 4 188 189 #if SPM_MM && defined(IMAGE_BL31) 190 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 191 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 50 192 #endif 193 194 /* 195 * PL011 related constants 196 */ 197 #define UART0_BASE 0x60000000 198 #define UART1_BASE 0x60030000 199 #define UART0_CLK_IN_HZ 1 200 #define UART1_CLK_IN_HZ 1 201 202 /* Secure UART */ 203 #define UART2_BASE 0x60040000 204 #define UART2_CLK_IN_HZ 1 205 206 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 207 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 208 209 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 210 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 211 212 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 213 214 #define QEMU_FLASH0_BASE 0x00000000 215 #define QEMU_FLASH0_SIZE 0x10000000 216 #define QEMU_FLASH1_BASE 0x10000000 217 #define QEMU_FLASH1_SIZE 0x10000000 218 219 #define PLAT_QEMU_FIP_BASE BL1_SIZE 220 #define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - BL1_SIZE) 221 222 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ 223 #define DEVICE0_BASE 0x40000000 224 #define DEVICE0_SIZE 0x04080000 225 /* This is map from NORMAL_UART up to SECURE_UART_MM */ 226 #define DEVICE1_BASE 0x60000000 227 #define DEVICE1_SIZE 0x10041000 228 /* This is a map for SECURE_EC */ 229 #define DEVICE2_BASE 0x50000000 230 #define DEVICE2_SIZE 0x00001000 231 232 /* 233 * GIC related constants 234 * We use GICv3 where CPU Interface registers are not memory mapped 235 * 236 * Legacy values - on platform version 0.1+ they are read from DT 237 */ 238 #define GICD_BASE 0x40060000 239 #define GICR_BASE 0x40080000 240 #define GICC_BASE 0x0 241 242 #define QEMU_IRQ_SEC_SGI_0 8 243 #define QEMU_IRQ_SEC_SGI_1 9 244 #define QEMU_IRQ_SEC_SGI_2 10 245 #define QEMU_IRQ_SEC_SGI_3 11 246 #define QEMU_IRQ_SEC_SGI_4 12 247 #define QEMU_IRQ_SEC_SGI_5 13 248 #define QEMU_IRQ_SEC_SGI_6 14 249 #define QEMU_IRQ_SEC_SGI_7 15 250 251 /****************************************************************************** 252 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 253 * interrupts. 254 *****************************************************************************/ 255 #define PLATFORM_G1S_PROPS(grp) \ 256 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 257 grp, GIC_INTR_CFG_EDGE), \ 258 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 259 grp, GIC_INTR_CFG_EDGE), \ 260 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 261 grp, GIC_INTR_CFG_EDGE), \ 262 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 263 grp, GIC_INTR_CFG_EDGE), \ 264 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 265 grp, GIC_INTR_CFG_EDGE), \ 266 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 267 grp, GIC_INTR_CFG_EDGE), \ 268 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 269 grp, GIC_INTR_CFG_EDGE), \ 270 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 271 grp, GIC_INTR_CFG_EDGE) 272 273 #define PLATFORM_G0_PROPS(grp) 274 275 /* 276 * DT related constants 277 */ 278 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 279 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 280 281 #if SPM_MM 282 #define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE 283 #define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000) 284 285 #ifdef IMAGE_BL2 286 /* In BL2 all memory allocated to the SPM Payload image is marked as RW. */ 287 # define QEMU_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 288 PLAT_QEMU_SP_IMAGE_BASE, \ 289 PLAT_QEMU_SP_IMAGE_SIZE, \ 290 MT_MEMORY | MT_RW | \ 291 MT_SECURE) 292 #elif IMAGE_BL31 293 /* All SPM Payload memory is marked as code in S-EL0 */ 294 # define QEMU_SP_IMAGE_MMAP MAP_REGION2(PLAT_QEMU_SP_IMAGE_BASE, \ 295 PLAT_QEMU_SP_IMAGE_BASE, \ 296 PLAT_QEMU_SP_IMAGE_SIZE, \ 297 MT_CODE | MT_SECURE | \ 298 MT_USER, \ 299 PAGE_SIZE) 300 #endif 301 302 /* 303 * EL3 -> S-EL0 secure shared memory 304 */ 305 #define PLAT_SPM_BUF_PCPU_SIZE ULL(0x10000) 306 #define PLAT_SPM_BUF_SIZE (PLATFORM_CORE_COUNT * \ 307 PLAT_SPM_BUF_PCPU_SIZE) 308 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - PLAT_SPM_BUF_SIZE) 309 310 #define QEMU_SPM_BUF_EL3_MMAP MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, \ 311 PLAT_SPM_BUF_SIZE, \ 312 MT_RW_DATA | MT_SECURE) 313 314 #define QEMU_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 315 PLAT_SPM_BUF_BASE, \ 316 PLAT_SPM_BUF_SIZE, \ 317 MT_RO_DATA | MT_SECURE | \ 318 MT_USER, \ 319 PAGE_SIZE) 320 321 /* 322 * Shared memory between Normal world and S-EL0 for 323 * passing data during service requests. It will be marked as RW and NS. 324 * This buffer is allocated at the top of NS_DRAM, the base address is 325 * overridden in SPM initialization. 326 */ 327 #define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \ 328 PLAT_QEMU_DT_MAX_SIZE) 329 #define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 330 331 #define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 332 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 333 PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \ 334 PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, \ 335 MT_RW_DATA | MT_NS | \ 336 MT_USER, \ 337 PAGE_SIZE) 338 339 #define PLAT_SP_IMAGE_NS_BUF_BASE PLAT_QEMU_SP_IMAGE_NS_BUF_BASE 340 #define PLAT_SP_IMAGE_NS_BUF_SIZE PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE 341 342 #define PLAT_QEMU_SP_IMAGE_HEAP_BASE (PLAT_QEMU_SP_IMAGE_BASE + \ 343 PLAT_QEMU_SP_IMAGE_SIZE) 344 #define PLAT_QEMU_SP_IMAGE_HEAP_SIZE ULL(0x800000) 345 346 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_QEMU_SP_IMAGE_HEAP_BASE + \ 347 PLAT_QEMU_SP_IMAGE_HEAP_SIZE) 348 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 349 #define QEMU_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 350 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 351 352 #define QEMU_SP_IMAGE_RW_MMAP MAP_REGION2( \ 353 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 354 PLAT_QEMU_SP_IMAGE_HEAP_BASE, \ 355 (QEMU_SP_IMAGE_STACK_TOTAL_SIZE + \ 356 PLAT_QEMU_SP_IMAGE_HEAP_SIZE), \ 357 MT_RW_DATA | MT_SECURE | \ 358 MT_USER, \ 359 PAGE_SIZE) 360 361 /* 362 * Secure variable storage is located at Secure Flash. 363 */ 364 #if SPM_MM 365 #define QEMU_SECURE_VARSTORE_BASE 0x01000000 366 #define QEMU_SECURE_VARSTORE_SIZE 0x00100000 367 #define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \ 368 QEMU_SECURE_VARSTORE_BASE, \ 369 QEMU_SECURE_VARSTORE_SIZE, \ 370 MT_DEVICE | MT_RW | \ 371 MT_SECURE | MT_USER) 372 #endif 373 374 /* Total number of memory regions with distinct properties */ 375 #define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6 376 377 /* 378 * Name of the section to put the translation tables used by the S-EL1/S-EL0 379 * context of a Secure Partition. 380 */ 381 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 382 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" 383 384 /* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/ 385 #define PLAT_SPM_COOKIE_0 ULL(0) 386 #define PLAT_SPM_COOKIE_1 ULL(0) 387 #endif 388 389 #define QEMU_PRI_BITS 2 390 #define PLAT_SP_PRI 0x20 391 392 #if !ENABLE_RME 393 #define RME_GPT_DRAM_SIZE 0 394 #define NS_DRAM0_BASE_OFFSET 0 395 #else /* !ENABLE_RME */ 396 /* 397 * SBSA RAM starts at 1TB and we support up to 1TB of RAM. As such we 398 * have 2TB of physical address space to cover. Since the GPT size can be 399 * 4GB, 64GB, 1TB, 4TB and so on, we need to select 4GB. Note that it is 400 * possible to support more than 1TB of RAM but that will take more room in 401 * secure memory due to the L1 GPTES. See PLAT_QEMU_L1_GPT_SIZE for details. 402 * 403 * 4TB / 1GB == 4096 GPTEs 404 * 4096 * 8 (bytes per GPTE) == 32768 i.e 8 pages 405 */ 406 #define PLAT_QEMU_L0_GPT_SIZE (8 * PAGE_SIZE) 407 #define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \ 408 (PLAT_QEMU_L0_GPT_SIZE + \ 409 PLAT_QEMU_GPT_BITLOCK_SIZE + \ 410 PLAT_QEMU_GPT_ALIGNMENT)) 411 412 #if RME_GPT_BITLOCK_BLOCK 413 /* 414 * 4TB / (RME_GPT_BITLOCK_BLOCK * 512M * 8) == 1024 415 */ 416 #define PLAT_QEMU_GPT_BITLOCK_SIZE (1 * PAGE_SIZE) 417 /* 418 * PLAT_QEMU_L0_GPT_SIZE is 8 pages and PLAT_QEMU_GPT_BITLOCK_SIZE 419 * is 1 page. As such we need 7 pages to have an 8 page alignment. 420 */ 421 #define PLAT_QEMU_GPT_ALIGNMENT (7 * PAGE_SIZE) 422 #else /* RME_GPT_BITLOCK_BLOCK */ 423 #define PLAT_QEMU_GPT_BITLOCK_SIZE 0 424 #define PLAT_QEMU_GPT_ALIGNMENT 0 425 #endif /* RME_GPT_BITLOCK_BLOCK */ 426 427 /* 428 * If we have 1TB of RAM and each L1GPT covers 1GB, we need 1024 L1GPTs. With 429 * one more L1GPT to cover the other physical address spaces (see pas_regions[] 430 * in qemu_bl31_setup.c), we need a total of 1025 L1GPTs. Each L1GPT is 131072 431 * bytes, so we need 1025 * 131072 bytes = 0x8020000 of RAM to hold the L1GPTS. 432 */ 433 #define PLAT_QEMU_L1_GPT_SIZE UL(0x08020000) 434 #define PLAT_QEMU_L1_GPT_BASE (BL_RAM_BASE + BL_RAM_SIZE - \ 435 PLAT_QEMU_L1_GPT_SIZE) 436 #define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \ 437 PLAT_QEMU_L1_GPT_SIZE - 1U) 438 439 #define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE 440 #define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \ 441 PLAT_QEMU_L0_GPT_SIZE + \ 442 PLAT_QEMU_GPT_BITLOCK_SIZE + \ 443 PLAT_QEMU_GPT_ALIGNMENT) 444 445 #ifndef __ASSEMBLER__ 446 /* L0 table greater than 4KB must be naturally aligned */ 447 CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0, 448 assert_l0_gpt_naturally_aligned); 449 #endif 450 451 /* Reserved some DRAM space for RMM (1072MB) */ 452 #define REALM_DRAM_BASE PLAT_QEMU_DRAM0_BASE 453 #define REALM_DRAM_SIZE 0x43000000 454 455 #define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE) 456 #define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 457 458 #define RMM_BASE (REALM_DRAM_BASE) 459 #define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE) 460 #define RMM_SHARED_BASE (RMM_LIMIT) 461 #define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE 462 463 #define MAP_GPT_L0_REGION MAP_REGION_FLAT( \ 464 PLAT_QEMU_L0_GPT_BASE, \ 465 (PLAT_QEMU_L0_GPT_SIZE + \ 466 PLAT_QEMU_GPT_BITLOCK_SIZE + \ 467 PLAT_QEMU_GPT_ALIGNMENT), \ 468 MT_MEMORY | MT_RW | EL3_PAS) 469 470 #define MAP_GPT_L1_REGION MAP_REGION_FLAT( \ 471 PLAT_QEMU_L1_GPT_BASE, \ 472 PLAT_QEMU_L1_GPT_SIZE, \ 473 MT_MEMORY | MT_RW | EL3_PAS) 474 /* 475 * We add the RMM_SHARED size to RMM mapping to map the region as a block. 476 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 477 */ 478 #define MAP_RMM_DRAM MAP_REGION_FLAT( \ 479 RMM_BASE, \ 480 (PLAT_QEMU_RMM_SIZE + \ 481 RMM_SHARED_SIZE), \ 482 MT_MEMORY | MT_RW | MT_REALM) 483 484 #define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \ 485 RMM_SHARED_BASE, \ 486 RMM_SHARED_SIZE, \ 487 MT_MEMORY | MT_RW | MT_REALM) 488 489 /* When RME is enabled, the base of NS DRAM is moved forward after the RMM */ 490 #define NS_DRAM0_BASE_OFFSET REALM_DRAM_SIZE 491 #endif /* !ENABLE_RME */ 492 493 #endif /* PLATFORM_DEF_H */ 494