1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/psci/psci.h> 13 #include <lib/semihosting.h> 14 #include <plat/common/platform.h> 15 #include <drivers/gpio.h> 16 17 #include "qemu_private.h" 18 19 #define ADP_STOPPED_APPLICATION_EXIT 0x20026 20 21 /* 22 * The secure entry point to be used on warm reset. 23 */ 24 static unsigned long secure_entrypoint; 25 26 /* Make composite power state parameter till power level 0 */ 27 #if PSCI_EXTENDED_STATE_ID 28 29 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 30 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 31 ((type) << PSTATE_TYPE_SHIFT)) 32 #else 33 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 34 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 35 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 36 ((type) << PSTATE_TYPE_SHIFT)) 37 #endif /* PSCI_EXTENDED_STATE_ID */ 38 39 40 #define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 41 (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ 42 qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 43 44 45 46 /* 47 * The table storing the valid idle power states. Ensure that the 48 * array entries are populated in ascending order of state-id to 49 * enable us to use binary search during power state validation. 50 * The table must be terminated by a NULL entry. 51 */ 52 static const unsigned int qemu_pm_idle_states[] = { 53 /* State-id - 0x01 */ 54 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, 55 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), 56 /* State-id - 0x02 */ 57 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, 58 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), 59 /* State-id - 0x22 */ 60 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, 61 MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), 62 0, 63 }; 64 65 /******************************************************************************* 66 * Platform handler called to check the validity of the power state 67 * parameter. The power state parameter has to be a composite power state. 68 ******************************************************************************/ 69 static int qemu_validate_power_state(unsigned int power_state, 70 psci_power_state_t *req_state) 71 { 72 unsigned int state_id; 73 int i; 74 75 assert(req_state); 76 77 /* 78 * Currently we are using a linear search for finding the matching 79 * entry in the idle power state array. This can be made a binary 80 * search if the number of entries justify the additional complexity. 81 */ 82 for (i = 0; !!qemu_pm_idle_states[i]; i++) { 83 if (power_state == qemu_pm_idle_states[i]) 84 break; 85 } 86 87 /* Return error if entry not found in the idle state array */ 88 if (!qemu_pm_idle_states[i]) 89 return PSCI_E_INVALID_PARAMS; 90 91 i = 0; 92 state_id = psci_get_pstate_id(power_state); 93 94 /* Parse the State ID and populate the state info parameter */ 95 while (state_id) { 96 req_state->pwr_domain_state[i++] = state_id & 97 PLAT_LOCAL_PSTATE_MASK; 98 state_id >>= PLAT_LOCAL_PSTATE_WIDTH; 99 } 100 101 return PSCI_E_SUCCESS; 102 } 103 104 /******************************************************************************* 105 * Platform handler called to check the validity of the non secure 106 * entrypoint. 107 ******************************************************************************/ 108 static int qemu_validate_ns_entrypoint(uintptr_t entrypoint) 109 { 110 /* 111 * Check if the non secure entrypoint lies within the non 112 * secure DRAM. 113 */ 114 if ((entrypoint >= NS_DRAM0_BASE) && 115 (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE))) 116 return PSCI_E_SUCCESS; 117 return PSCI_E_INVALID_ADDRESS; 118 } 119 120 /******************************************************************************* 121 * Platform handler called when a CPU is about to enter standby. 122 ******************************************************************************/ 123 static void qemu_cpu_standby(plat_local_state_t cpu_state) 124 { 125 126 assert(cpu_state == PLAT_LOCAL_STATE_RET); 127 128 /* 129 * Enter standby state 130 * dsb is good practice before using wfi to enter low power states 131 */ 132 dsb(); 133 wfi(); 134 } 135 136 /******************************************************************************* 137 * Platform handler called when a power domain is about to be turned on. The 138 * mpidr determines the CPU to be turned on. 139 ******************************************************************************/ 140 static int qemu_pwr_domain_on(u_register_t mpidr) 141 { 142 int rc = PSCI_E_SUCCESS; 143 unsigned pos = plat_core_pos_by_mpidr(mpidr); 144 uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; 145 146 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; 147 sev(); 148 149 return rc; 150 } 151 152 /******************************************************************************* 153 * Platform handler called when a power domain is about to be turned off. The 154 * target_state encodes the power state that each level should transition to. 155 ******************************************************************************/ 156 static void qemu_pwr_domain_off(const psci_power_state_t *target_state) 157 { 158 qemu_pwr_gic_off(); 159 } 160 161 void __dead2 plat_secondary_cold_boot_setup(void); 162 163 static void __dead2 164 qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 165 { 166 disable_mmu_el3(); 167 plat_secondary_cold_boot_setup(); 168 } 169 170 /******************************************************************************* 171 * Platform handler called when a power domain is about to be suspended. The 172 * target_state encodes the power state that each level should transition to. 173 ******************************************************************************/ 174 void qemu_pwr_domain_suspend(const psci_power_state_t *target_state) 175 { 176 assert(0); 177 } 178 179 /******************************************************************************* 180 * Platform handler called when a power domain has just been powered on after 181 * being turned off earlier. The target_state encodes the low power state that 182 * each level has woken up from. 183 ******************************************************************************/ 184 void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) 185 { 186 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 187 PLAT_LOCAL_STATE_OFF); 188 189 qemu_pwr_gic_on_finish(); 190 } 191 192 /******************************************************************************* 193 * Platform handler called when a power domain has just been powered on after 194 * having been suspended earlier. The target_state encodes the low power state 195 * that each level has woken up from. 196 ******************************************************************************/ 197 void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 198 { 199 assert(0); 200 } 201 202 /******************************************************************************* 203 * Platform handlers to shutdown/reboot the system 204 ******************************************************************************/ 205 206 static void __dead2 qemu_system_off(void) 207 { 208 #ifdef SECURE_GPIO_BASE 209 ERROR("QEMU System Power off: with GPIO.\n"); 210 gpio_set_direction(SECURE_GPIO_POWEROFF, GPIO_DIR_OUT); 211 gpio_set_value(SECURE_GPIO_POWEROFF, GPIO_LEVEL_LOW); 212 gpio_set_value(SECURE_GPIO_POWEROFF, GPIO_LEVEL_HIGH); 213 #else 214 semihosting_exit(ADP_STOPPED_APPLICATION_EXIT, 0); 215 ERROR("QEMU System Off: semihosting call unexpectedly returned.\n"); 216 #endif 217 panic(); 218 } 219 220 static void __dead2 qemu_system_reset(void) 221 { 222 ERROR("QEMU System Reset: with GPIO.\n"); 223 #ifdef SECURE_GPIO_BASE 224 gpio_set_direction(SECURE_GPIO_RESET, GPIO_DIR_OUT); 225 gpio_set_value(SECURE_GPIO_RESET, GPIO_LEVEL_LOW); 226 gpio_set_value(SECURE_GPIO_RESET, GPIO_LEVEL_HIGH); 227 #else 228 ERROR("QEMU System Reset: operation not handled.\n"); 229 #endif 230 panic(); 231 } 232 233 static const plat_psci_ops_t plat_qemu_psci_pm_ops = { 234 .cpu_standby = qemu_cpu_standby, 235 .pwr_domain_on = qemu_pwr_domain_on, 236 .pwr_domain_off = qemu_pwr_domain_off, 237 .pwr_domain_pwr_down_wfi = qemu_pwr_domain_pwr_down_wfi, 238 .pwr_domain_suspend = qemu_pwr_domain_suspend, 239 .pwr_domain_on_finish = qemu_pwr_domain_on_finish, 240 .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, 241 .system_off = qemu_system_off, 242 .system_reset = qemu_system_reset, 243 .validate_power_state = qemu_validate_power_state, 244 .validate_ns_entrypoint = qemu_validate_ns_entrypoint 245 }; 246 247 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 248 const plat_psci_ops_t **psci_ops) 249 { 250 uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; 251 252 *mailbox = sec_entrypoint; 253 secure_entrypoint = (unsigned long) sec_entrypoint; 254 *psci_ops = &plat_qemu_psci_pm_ops; 255 256 return 0; 257 } 258