1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/psci/psci.h> 13 #include <lib/semihosting.h> 14 #include <plat/common/platform.h> 15 #include <drivers/gpio.h> 16 17 #include "qemu_private.h" 18 19 #define ADP_STOPPED_APPLICATION_EXIT 0x20026 20 21 /* 22 * The secure entry point to be used on warm reset. 23 */ 24 static unsigned long secure_entrypoint; 25 26 /* Make composite power state parameter till power level 0 */ 27 #if PSCI_EXTENDED_STATE_ID 28 29 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 30 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 31 ((type) << PSTATE_TYPE_SHIFT)) 32 #else 33 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 34 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 35 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 36 ((type) << PSTATE_TYPE_SHIFT)) 37 #endif /* PSCI_EXTENDED_STATE_ID */ 38 39 40 #define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 41 (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ 42 qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 43 44 45 46 /* 47 * The table storing the valid idle power states. Ensure that the 48 * array entries are populated in ascending order of state-id to 49 * enable us to use binary search during power state validation. 50 * The table must be terminated by a NULL entry. 51 */ 52 static const unsigned int qemu_pm_idle_states[] = { 53 /* State-id - 0x01 */ 54 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, 55 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), 56 /* State-id - 0x02 */ 57 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, 58 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), 59 /* State-id - 0x22 */ 60 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, 61 MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), 62 0, 63 }; 64 65 /******************************************************************************* 66 * Platform handler called to check the validity of the power state 67 * parameter. The power state parameter has to be a composite power state. 68 ******************************************************************************/ 69 static int qemu_validate_power_state(unsigned int power_state, 70 psci_power_state_t *req_state) 71 { 72 unsigned int state_id; 73 int i; 74 75 assert(req_state); 76 77 /* 78 * Currently we are using a linear search for finding the matching 79 * entry in the idle power state array. This can be made a binary 80 * search if the number of entries justify the additional complexity. 81 */ 82 for (i = 0; !!qemu_pm_idle_states[i]; i++) { 83 if (power_state == qemu_pm_idle_states[i]) 84 break; 85 } 86 87 /* Return error if entry not found in the idle state array */ 88 if (!qemu_pm_idle_states[i]) 89 return PSCI_E_INVALID_PARAMS; 90 91 i = 0; 92 state_id = psci_get_pstate_id(power_state); 93 94 /* Parse the State ID and populate the state info parameter */ 95 while (state_id) { 96 req_state->pwr_domain_state[i++] = state_id & 97 PLAT_LOCAL_PSTATE_MASK; 98 state_id >>= PLAT_LOCAL_PSTATE_WIDTH; 99 } 100 101 return PSCI_E_SUCCESS; 102 } 103 104 /******************************************************************************* 105 * Platform handler called when a CPU is about to enter standby. 106 ******************************************************************************/ 107 static void qemu_cpu_standby(plat_local_state_t cpu_state) 108 { 109 110 assert(cpu_state == PLAT_LOCAL_STATE_RET); 111 112 /* 113 * Enter standby state 114 * dsb is good practice before using wfi to enter low power states 115 */ 116 dsb(); 117 wfi(); 118 } 119 120 /******************************************************************************* 121 * Platform handler called when a power domain is about to be turned on. The 122 * mpidr determines the CPU to be turned on. 123 ******************************************************************************/ 124 static int qemu_pwr_domain_on(u_register_t mpidr) 125 { 126 int rc = PSCI_E_SUCCESS; 127 unsigned pos = plat_core_pos_by_mpidr(mpidr); 128 uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; 129 130 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; 131 sev(); 132 133 return rc; 134 } 135 136 /******************************************************************************* 137 * Platform handler called when a power domain is about to be turned off. The 138 * target_state encodes the power state that each level should transition to. 139 ******************************************************************************/ 140 static void qemu_pwr_domain_off(const psci_power_state_t *target_state) 141 { 142 qemu_pwr_gic_off(); 143 } 144 145 void __dead2 plat_secondary_cold_boot_setup(void); 146 147 static void __dead2 148 qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 149 { 150 disable_mmu_el3(); 151 plat_secondary_cold_boot_setup(); 152 } 153 154 /******************************************************************************* 155 * Platform handler called when a power domain is about to be suspended. The 156 * target_state encodes the power state that each level should transition to. 157 ******************************************************************************/ 158 void qemu_pwr_domain_suspend(const psci_power_state_t *target_state) 159 { 160 assert(0); 161 } 162 163 /******************************************************************************* 164 * Platform handler called when a power domain has just been powered on after 165 * being turned off earlier. The target_state encodes the low power state that 166 * each level has woken up from. 167 ******************************************************************************/ 168 void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) 169 { 170 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 171 PLAT_LOCAL_STATE_OFF); 172 173 qemu_pwr_gic_on_finish(); 174 } 175 176 /******************************************************************************* 177 * Platform handler called when a power domain has just been powered on after 178 * having been suspended earlier. The target_state encodes the low power state 179 * that each level has woken up from. 180 ******************************************************************************/ 181 void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 182 { 183 assert(0); 184 } 185 186 /******************************************************************************* 187 * Platform handlers to shutdown/reboot the system 188 ******************************************************************************/ 189 190 static void __dead2 qemu_system_off(void) 191 { 192 #ifdef SECURE_GPIO_BASE 193 ERROR("QEMU System Power off: with GPIO.\n"); 194 gpio_set_direction(SECURE_GPIO_POWEROFF, GPIO_DIR_OUT); 195 gpio_set_value(SECURE_GPIO_POWEROFF, GPIO_LEVEL_LOW); 196 gpio_set_value(SECURE_GPIO_POWEROFF, GPIO_LEVEL_HIGH); 197 #else 198 semihosting_exit(ADP_STOPPED_APPLICATION_EXIT, 0); 199 ERROR("QEMU System Off: semihosting call unexpectedly returned.\n"); 200 #endif 201 panic(); 202 } 203 204 static void __dead2 qemu_system_reset(void) 205 { 206 ERROR("QEMU System Reset: with GPIO.\n"); 207 #ifdef SECURE_GPIO_BASE 208 gpio_set_direction(SECURE_GPIO_RESET, GPIO_DIR_OUT); 209 gpio_set_value(SECURE_GPIO_RESET, GPIO_LEVEL_LOW); 210 gpio_set_value(SECURE_GPIO_RESET, GPIO_LEVEL_HIGH); 211 #else 212 ERROR("QEMU System Reset: operation not handled.\n"); 213 #endif 214 panic(); 215 } 216 217 static const plat_psci_ops_t plat_qemu_psci_pm_ops = { 218 .cpu_standby = qemu_cpu_standby, 219 .pwr_domain_on = qemu_pwr_domain_on, 220 .pwr_domain_off = qemu_pwr_domain_off, 221 .pwr_domain_pwr_down_wfi = qemu_pwr_domain_pwr_down_wfi, 222 .pwr_domain_suspend = qemu_pwr_domain_suspend, 223 .pwr_domain_on_finish = qemu_pwr_domain_on_finish, 224 .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, 225 .system_off = qemu_system_off, 226 .system_reset = qemu_system_reset, 227 .validate_power_state = qemu_validate_power_state, 228 }; 229 230 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 231 const plat_psci_ops_t **psci_ops) 232 { 233 uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; 234 235 *mailbox = sec_entrypoint; 236 secure_entrypoint = (unsigned long) sec_entrypoint; 237 *psci_ops = &plat_qemu_psci_pm_ops; 238 239 return 0; 240 } 241