1 2 /* 3 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <platform_def.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 #include <services/el3_spmc_ffa_memory.h> 14 #if ENABLE_RME 15 #include <services/rmm_core_manifest.h> 16 #endif 17 18 #include <plat/common/platform.h> 19 #include "qemu_private.h" 20 21 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 22 DEVICE0_SIZE, \ 23 MT_DEVICE | MT_RW | EL3_PAS) 24 25 #ifdef DEVICE1_BASE 26 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 27 DEVICE1_SIZE, \ 28 MT_DEVICE | MT_RW | EL3_PAS) 29 #endif 30 31 #ifdef DEVICE2_BASE 32 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 33 DEVICE2_SIZE, \ 34 MT_DEVICE | MT_RW | EL3_PAS) 35 #endif 36 37 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ 38 SHARED_RAM_SIZE, \ 39 MT_DEVICE | MT_RW | EL3_PAS) 40 41 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ 42 MT_MEMORY | MT_RW | EL3_PAS) 43 44 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ 45 MT_MEMORY | MT_RW | MT_NS) 46 47 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ 48 MT_MEMORY | MT_RO | EL3_PAS) 49 50 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ 51 MT_MEMORY | MT_RO | EL3_PAS) 52 53 #ifdef FW_HANDOFF_BASE 54 #define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \ 55 MT_MEMORY | MT_RW | EL3_PAS) 56 #endif 57 #ifdef FW_NS_HANDOFF_BASE 58 #define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE, \ 59 MT_MEMORY | MT_RW | MT_NS) 60 #endif 61 /* 62 * Table of regions for various BL stages to map using the MMU. 63 * This doesn't include TZRAM as the 'mem_layout' argument passed to 64 * arm_configure_mmu_elx() will give the available subset of that, 65 */ 66 #ifdef IMAGE_BL1 67 static const mmap_region_t plat_qemu_mmap[] = { 68 MAP_FLASH0, 69 MAP_FLASH1, 70 MAP_SHARED_RAM, 71 MAP_DEVICE0, 72 #ifdef MAP_DEVICE1 73 MAP_DEVICE1, 74 #endif 75 #ifdef MAP_DEVICE2 76 MAP_DEVICE2, 77 #endif 78 {0} 79 }; 80 #endif 81 #ifdef IMAGE_BL2 82 static const mmap_region_t plat_qemu_mmap[] = { 83 MAP_FLASH0, 84 MAP_FLASH1, 85 MAP_SHARED_RAM, 86 MAP_DEVICE0, 87 #ifdef MAP_DEVICE1 88 MAP_DEVICE1, 89 #endif 90 #ifdef MAP_DEVICE2 91 MAP_DEVICE2, 92 #endif 93 MAP_NS_DRAM0, 94 #if SPM_MM 95 QEMU_SP_IMAGE_MMAP, 96 #else 97 MAP_BL32_MEM, 98 #endif 99 #ifdef MAP_FW_HANDOFF 100 MAP_FW_HANDOFF, 101 #endif 102 {0} 103 }; 104 #endif 105 #ifdef IMAGE_BL31 106 static const mmap_region_t plat_qemu_mmap[] = { 107 MAP_SHARED_RAM, 108 MAP_DEVICE0, 109 #ifdef MAP_DEVICE1 110 MAP_DEVICE1, 111 #endif 112 #ifdef MAP_DEVICE2 113 MAP_DEVICE2, 114 #endif 115 #ifdef MAP_FW_HANDOFF 116 MAP_FW_HANDOFF, 117 #endif 118 #ifdef MAP_FW_NS_HANDOFF 119 MAP_FW_NS_HANDOFF, 120 #endif 121 #if SPM_MM 122 MAP_NS_DRAM0, 123 QEMU_SPM_BUF_EL3_MMAP, 124 #elif !SPMC_AT_EL3 125 MAP_BL32_MEM, 126 #endif 127 {0} 128 }; 129 #endif 130 #ifdef IMAGE_BL32 131 static const mmap_region_t plat_qemu_mmap[] = { 132 MAP_SHARED_RAM, 133 MAP_DEVICE0, 134 #ifdef MAP_DEVICE1 135 MAP_DEVICE1, 136 #endif 137 #ifdef MAP_DEVICE2 138 MAP_DEVICE2, 139 #endif 140 {0} 141 }; 142 #endif 143 144 #ifdef IMAGE_RMM 145 const mmap_region_t plat_qemu_mmap[] = { 146 MAP_DEVICE0, 147 #ifdef MAP_DEVICE1 148 MAP_DEVICE1, 149 #endif 150 #ifdef MAP_DEVICE2 151 MAP_DEVICE2, 152 #endif 153 {0} 154 }; 155 #endif 156 157 /******************************************************************************* 158 * Returns QEMU platform specific memory map regions. 159 ******************************************************************************/ 160 const mmap_region_t *plat_qemu_get_mmap(void) 161 { 162 return plat_qemu_mmap; 163 } 164 165 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT 166 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 167 { 168 return get_mbedtls_heap_helper(heap_addr, heap_size); 169 } 170 #endif 171 172 #if SPMC_AT_EL3 173 /* 174 * When using the EL3 SPMC implementation allocate the datastore 175 * for tracking shared memory descriptors in normal memory. 176 */ 177 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024 178 179 uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE]; 180 181 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 182 { 183 *datastore = plat_spmc_shmem_datastore; 184 *size = PLAT_SPMC_SHMEM_DATASTORE_SIZE; 185 return 0; 186 } 187 188 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 189 { 190 return 0; 191 } 192 193 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 194 { 195 return 0; 196 } 197 #endif 198 199 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 200 /* 201 * A dummy implementation of the platform handler for Group0 secure interrupt. 202 */ 203 int plat_spmd_handle_group0_interrupt(uint32_t intid) 204 { 205 (void)intid; 206 return -1; 207 } 208 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 209 210 #if ENABLE_RME 211 /* 212 * Get a pointer to the RMM-EL3 Shared buffer and return it 213 * through the pointer passed as parameter. 214 * 215 * This function returns the size of the shared buffer. 216 */ 217 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) 218 { 219 *shared = (uintptr_t)RMM_SHARED_BASE; 220 221 return (size_t)RMM_SHARED_SIZE; 222 } 223 224 int plat_rmmd_load_manifest(struct rmm_manifest *manifest) 225 { 226 uint64_t checksum; 227 uintptr_t base; 228 uint64_t size; 229 struct ns_dram_bank *bank_ptr; 230 231 assert(manifest != NULL); 232 233 manifest->version = RMMD_MANIFEST_VERSION; 234 manifest->padding = 0U; /* RES0 */ 235 manifest->plat_data = (uintptr_t)NULL; 236 manifest->plat_dram.num_banks = 1; 237 238 /* 239 * Array ns_dram_banks[] follows ns_dram_info structure: 240 * 241 * +-----------------------------------+ 242 * | offset | field | comment | 243 * +----------+-----------+------------+ 244 * | 0 | version | 0x00000002 | 245 * +----------+-----------+------------+ 246 * | 4 | padding | 0x00000000 | 247 * +----------+-----------+------------+ 248 * | 8 | plat_data | NULL | 249 * +----------+-----------+------------+ 250 * | 16 | num_banks | | 251 * +----------+-----------+ | 252 * | 24 | banks | plat_dram | 253 * +----------+-----------+ | 254 * | 32 | checksum | | 255 * +----------+-----------+------------+ 256 * | 40 | base 0 | | 257 * +----------+-----------+ bank[0] | 258 * | 48 | size 0 | | 259 * +----------+-----------+------------+ 260 */ 261 bank_ptr = (struct ns_dram_bank *) 262 ((uintptr_t)&manifest->plat_dram.checksum + 263 sizeof(manifest->plat_dram.checksum)); 264 265 manifest->plat_dram.banks = bank_ptr; 266 267 /* Calculate checksum of plat_dram structure */ 268 checksum = 1 + (uint64_t)bank_ptr; 269 270 base = NS_DRAM0_BASE; 271 size = NS_DRAM0_SIZE; 272 bank_ptr[0].base = base; 273 bank_ptr[0].size = size; 274 checksum += base + size; 275 276 /* Checksum must be 0 */ 277 manifest->plat_dram.checksum = ~checksum + 1UL; 278 279 return 0; 280 } 281 #endif /* ENABLE_RME */ 282