1 2 /* 3 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <platform_def.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 14 #include "qemu_private.h" 15 16 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 17 DEVICE0_SIZE, \ 18 MT_DEVICE | MT_RW | MT_SECURE) 19 20 #ifdef DEVICE1_BASE 21 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 22 DEVICE1_SIZE, \ 23 MT_DEVICE | MT_RW | MT_SECURE) 24 #endif 25 26 #ifdef DEVICE2_BASE 27 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 28 DEVICE2_SIZE, \ 29 MT_DEVICE | MT_RO | MT_SECURE) 30 #endif 31 32 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ 33 SHARED_RAM_SIZE, \ 34 MT_DEVICE | MT_RW | MT_SECURE) 35 36 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ 37 MT_MEMORY | MT_RW | MT_SECURE) 38 39 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ 40 MT_MEMORY | MT_RW | MT_NS) 41 42 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ 43 MT_MEMORY | MT_RO | MT_SECURE) 44 45 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ 46 MT_MEMORY | MT_RO | MT_SECURE) 47 48 /* 49 * Table of regions for various BL stages to map using the MMU. 50 * This doesn't include TZRAM as the 'mem_layout' argument passed to 51 * arm_configure_mmu_elx() will give the available subset of that, 52 */ 53 #ifdef IMAGE_BL1 54 static const mmap_region_t plat_qemu_mmap[] = { 55 MAP_FLASH0, 56 MAP_FLASH1, 57 MAP_SHARED_RAM, 58 MAP_DEVICE0, 59 #ifdef MAP_DEVICE1 60 MAP_DEVICE1, 61 #endif 62 #ifdef MAP_DEVICE2 63 MAP_DEVICE2, 64 #endif 65 {0} 66 }; 67 #endif 68 #ifdef IMAGE_BL2 69 static const mmap_region_t plat_qemu_mmap[] = { 70 MAP_FLASH0, 71 MAP_FLASH1, 72 MAP_SHARED_RAM, 73 MAP_DEVICE0, 74 #ifdef MAP_DEVICE1 75 MAP_DEVICE1, 76 #endif 77 #ifdef MAP_DEVICE2 78 MAP_DEVICE2, 79 #endif 80 MAP_NS_DRAM0, 81 #if SPM_MM 82 QEMU_SP_IMAGE_MMAP, 83 #else 84 MAP_BL32_MEM, 85 #endif 86 {0} 87 }; 88 #endif 89 #ifdef IMAGE_BL31 90 static const mmap_region_t plat_qemu_mmap[] = { 91 MAP_SHARED_RAM, 92 MAP_DEVICE0, 93 #ifdef MAP_DEVICE1 94 MAP_DEVICE1, 95 #endif 96 #if SPM_MM 97 QEMU_SPM_BUF_EL3_MMAP, 98 #else 99 MAP_BL32_MEM, 100 #endif 101 {0} 102 }; 103 #endif 104 #ifdef IMAGE_BL32 105 static const mmap_region_t plat_qemu_mmap[] = { 106 MAP_SHARED_RAM, 107 MAP_DEVICE0, 108 #ifdef MAP_DEVICE1 109 MAP_DEVICE1, 110 #endif 111 {0} 112 }; 113 #endif 114 115 /******************************************************************************* 116 * Macro generating the code for the function setting up the pagetables as per 117 * the platform memory map & initialize the mmu, for the given exception level 118 ******************************************************************************/ 119 120 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 121 void qemu_configure_mmu_##_el(unsigned long total_base, \ 122 unsigned long total_size, \ 123 unsigned long code_start, \ 124 unsigned long code_limit, \ 125 unsigned long ro_start, \ 126 unsigned long ro_limit, \ 127 unsigned long coh_start, \ 128 unsigned long coh_limit) \ 129 { \ 130 mmap_add_region(total_base, total_base, \ 131 total_size, \ 132 MT_MEMORY | MT_RW | MT_SECURE); \ 133 mmap_add_region(code_start, code_start, \ 134 code_limit - code_start, \ 135 MT_CODE | MT_SECURE); \ 136 mmap_add_region(ro_start, ro_start, \ 137 ro_limit - ro_start, \ 138 MT_RO_DATA | MT_SECURE); \ 139 mmap_add_region(coh_start, coh_start, \ 140 coh_limit - coh_start, \ 141 MT_DEVICE | MT_RW | MT_SECURE); \ 142 mmap_add(plat_qemu_mmap); \ 143 init_xlat_tables(); \ 144 \ 145 enable_mmu_##_el(0); \ 146 } 147 148 /* Define EL1 and EL3 variants of the function initialising the MMU */ 149 #ifdef __aarch64__ 150 DEFINE_CONFIGURE_MMU_EL(el1) 151 DEFINE_CONFIGURE_MMU_EL(el3) 152 #else 153 DEFINE_CONFIGURE_MMU_EL(svc_mon) 154 #endif 155 156 157