1 2 /* 3 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <services/el3_spmc_ffa_memory.h> 16 #if ENABLE_RME 17 #include <services/rmm_core_manifest.h> 18 #endif 19 #ifdef PLAT_qemu_sbsa 20 #include <sbsa_platform.h> 21 #endif 22 23 #include <plat/common/platform.h> 24 #include "qemu_private.h" 25 26 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 27 DEVICE0_SIZE, \ 28 MT_DEVICE | MT_RW | EL3_PAS) 29 30 #ifdef DEVICE1_BASE 31 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 32 DEVICE1_SIZE, \ 33 MT_DEVICE | MT_RW | EL3_PAS) 34 #endif 35 36 #ifdef DEVICE2_BASE 37 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 38 DEVICE2_SIZE, \ 39 MT_DEVICE | MT_RW | EL3_PAS) 40 #endif 41 42 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ 43 SHARED_RAM_SIZE, \ 44 MT_DEVICE | MT_RW | EL3_PAS) 45 46 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ 47 MT_MEMORY | MT_RW | EL3_PAS) 48 49 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ 50 MT_MEMORY | MT_RW | MT_NS) 51 52 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ 53 MT_MEMORY | MT_RO | EL3_PAS) 54 55 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ 56 MT_MEMORY | MT_RO | EL3_PAS) 57 58 #ifdef FW_HANDOFF_BASE 59 #define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \ 60 MT_MEMORY | MT_RW | EL3_PAS) 61 #endif 62 #ifdef FW_NS_HANDOFF_BASE 63 #define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE, \ 64 MT_MEMORY | MT_RW | MT_NS) 65 #endif 66 /* 67 * Table of regions for various BL stages to map using the MMU. 68 * This doesn't include TZRAM as the 'mem_layout' argument passed to 69 * arm_configure_mmu_elx() will give the available subset of that, 70 */ 71 #ifdef IMAGE_BL1 72 static const mmap_region_t plat_qemu_mmap[] = { 73 MAP_FLASH0, 74 MAP_FLASH1, 75 MAP_SHARED_RAM, 76 MAP_DEVICE0, 77 #ifdef MAP_DEVICE1 78 MAP_DEVICE1, 79 #endif 80 #ifdef MAP_DEVICE2 81 MAP_DEVICE2, 82 #endif 83 {0} 84 }; 85 #endif 86 #ifdef IMAGE_BL2 87 static const mmap_region_t plat_qemu_mmap[] = { 88 MAP_FLASH0, 89 MAP_FLASH1, 90 MAP_SHARED_RAM, 91 MAP_DEVICE0, 92 #ifdef MAP_DEVICE1 93 MAP_DEVICE1, 94 #endif 95 #ifdef MAP_DEVICE2 96 MAP_DEVICE2, 97 #endif 98 MAP_NS_DRAM0, 99 #if SPM_MM 100 QEMU_SP_IMAGE_MMAP, 101 #else 102 MAP_BL32_MEM, 103 #endif 104 #ifdef MAP_FW_HANDOFF 105 MAP_FW_HANDOFF, 106 #endif 107 {0} 108 }; 109 #endif 110 #ifdef IMAGE_BL31 111 static const mmap_region_t plat_qemu_mmap[] = { 112 MAP_SHARED_RAM, 113 MAP_DEVICE0, 114 #ifdef MAP_DEVICE1 115 MAP_DEVICE1, 116 #endif 117 #ifdef MAP_DEVICE2 118 MAP_DEVICE2, 119 #endif 120 #ifdef MAP_FW_HANDOFF 121 MAP_FW_HANDOFF, 122 #endif 123 #ifdef MAP_FW_NS_HANDOFF 124 MAP_FW_NS_HANDOFF, 125 #endif 126 #if SPM_MM 127 MAP_NS_DRAM0, 128 QEMU_SPM_BUF_EL3_MMAP, 129 #elif !SPMC_AT_EL3 130 MAP_BL32_MEM, 131 #endif 132 {0} 133 }; 134 #endif 135 #ifdef IMAGE_BL32 136 static const mmap_region_t plat_qemu_mmap[] = { 137 MAP_SHARED_RAM, 138 MAP_DEVICE0, 139 #ifdef MAP_DEVICE1 140 MAP_DEVICE1, 141 #endif 142 #ifdef MAP_DEVICE2 143 MAP_DEVICE2, 144 #endif 145 {0} 146 }; 147 #endif 148 149 #ifdef IMAGE_RMM 150 const mmap_region_t plat_qemu_mmap[] = { 151 MAP_DEVICE0, 152 #ifdef MAP_DEVICE1 153 MAP_DEVICE1, 154 #endif 155 #ifdef MAP_DEVICE2 156 MAP_DEVICE2, 157 #endif 158 {0} 159 }; 160 #endif 161 162 /******************************************************************************* 163 * Returns QEMU platform specific memory map regions. 164 ******************************************************************************/ 165 const mmap_region_t *plat_qemu_get_mmap(void) 166 { 167 return plat_qemu_mmap; 168 } 169 170 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT 171 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 172 { 173 return get_mbedtls_heap_helper(heap_addr, heap_size); 174 } 175 #endif 176 177 #if SPMC_AT_EL3 178 /* 179 * When using the EL3 SPMC implementation allocate the datastore 180 * for tracking shared memory descriptors in normal memory. 181 */ 182 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024 183 184 uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE] __aligned(2 * sizeof(long)); 185 186 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 187 { 188 *datastore = plat_spmc_shmem_datastore; 189 *size = PLAT_SPMC_SHMEM_DATASTORE_SIZE; 190 return 0; 191 } 192 193 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 194 { 195 return 0; 196 } 197 198 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 199 { 200 return 0; 201 } 202 #endif 203 204 #if defined(SPD_spmd) 205 int plat_spmd_handle_group0_interrupt(uint32_t intid) 206 { 207 /* 208 * Currently, there are no sources of Group0 secure interrupt 209 * enabled for QEMU. 210 */ 211 (void)intid; 212 return -1; 213 } 214 #endif /*defined(SPD_spmd)*/ 215 216 #if ENABLE_RME 217 /* 218 * Get a pointer to the RMM-EL3 Shared buffer and return it 219 * through the pointer passed as parameter. 220 * 221 * This function returns the size of the shared buffer. 222 */ 223 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) 224 { 225 *shared = (uintptr_t)RMM_SHARED_BASE; 226 227 return (size_t)RMM_SHARED_SIZE; 228 } 229 230 #ifdef PLAT_qemu 231 static uint32_t plat_get_num_memnodes(void) 232 { 233 return 1; 234 } 235 236 static void plat_get_memory_node(int index, struct ns_dram_bank *bank_ptr) 237 { 238 (void) index; 239 bank_ptr->base = NS_DRAM0_BASE; 240 bank_ptr->size = NS_DRAM0_SIZE; 241 } 242 #elif PLAT_qemu_sbsa 243 static uint32_t plat_get_num_memnodes(void) 244 { 245 return sbsa_platform_num_memnodes(); 246 } 247 248 static void plat_get_memory_node(int index, struct ns_dram_bank *bank_ptr) 249 { 250 struct platform_memory_data data = {0, 0, 0}; 251 252 if (index < sbsa_platform_num_memnodes()) { 253 data = sbsa_platform_memory_node(index); 254 } 255 256 bank_ptr->base = data.addr_base; 257 bank_ptr->size = data.addr_size; 258 } 259 #endif /* PLAT_qemu */ 260 261 int plat_rmmd_load_manifest(struct rmm_manifest *manifest) 262 { 263 int i, last; 264 uint64_t checksum; 265 size_t num_banks = plat_get_num_memnodes(); 266 size_t num_consoles = 1; 267 struct ns_dram_bank *bank_ptr; 268 struct console_info *console_ptr; 269 270 assert(manifest != NULL); 271 272 manifest->version = RMMD_MANIFEST_VERSION; 273 manifest->padding = 0U; /* RES0 */ 274 manifest->plat_data = (uintptr_t)NULL; 275 manifest->plat_dram.num_banks = num_banks; 276 manifest->plat_console.num_consoles = num_consoles; 277 278 /* 279 * Boot manifest structure illustration: 280 * 281 * +----------------------------------------+ 282 * | offset | field | comment | 283 * +----------+--------------+--------------+ 284 * | 0 | version | 0x00000003 | 285 * +----------+--------------+--------------+ 286 * | 4 | padding | 0x00000000 | 287 * +----------+--------------+--------------+ 288 * | 8 | plat_data | NULL | 289 * +----------+--------------+--------------+ 290 * | 16 | num_banks | | 291 * +----------+--------------+ | 292 * | 24 | banks | plat_dram | 293 * +----------+--------------+ | 294 * | 32 | checksum | | 295 * +----------+--------------+--------------+ 296 * | 40 | num_consoles | | 297 * +----------+--------------+ | 298 * | 48 | consoles | plat_console | 299 * +----------+--------------+ | 300 * | 56 | checksum | | 301 * +----------+--------------+--------------+ 302 * | 64 | base 0 | | 303 * +----------+--------------+ bank[0] | 304 * | 72 | size 0 | | 305 * +----------+--------------+--------------+ 306 * | 80 | base | | 307 * +----------+--------------+ | 308 * | 88 | map_pages | | 309 * +----------+--------------+ | 310 * | 96 | name | | 311 * +----------+--------------+ consoles[0] | 312 * | 104 | clk_in_hz | | 313 * +----------+--------------+ | 314 * | 112 | baud_rate | | 315 * +----------+--------------+ | 316 * | 120 | flags | | 317 * +----------+--------------+--------------+ 318 */ 319 bank_ptr = (struct ns_dram_bank *) 320 (((uintptr_t)manifest) + sizeof(*manifest)); 321 322 console_ptr = (struct console_info *) 323 ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr))); 324 325 manifest->plat_dram.banks = bank_ptr; 326 manifest->plat_console.consoles = console_ptr; 327 328 /* Ensure the manifest is not larger than the shared buffer */ 329 assert((sizeof(struct rmm_manifest) + 330 (sizeof(struct console_info) * num_consoles) + 331 (sizeof(struct ns_dram_bank) * num_banks)) <= RMM_SHARED_SIZE); 332 333 /* Calculate checksum of plat_dram structure */ 334 checksum = num_banks + (uint64_t)bank_ptr; 335 336 /* 337 * In the TF-A, NUMA nodes (if present) are stored in descending 338 * order, i.e: 339 * 340 * INFO: RAM 0: node-id: 1, address: 0x10080000000 - 0x101ffffffff 341 * INFO: RAM 1: node-id: 0, address: 0x10043000000 - 0x1007fffffff 342 * 343 * The RMM expects the memory banks to be presented in ascending order: 344 * 345 * INFO: RAM 1: node-id: 0, address: 0x10043000000 - 0x1007fffffff 346 * INFO: RAM 0: node-id: 1, address: 0x10080000000 - 0x101ffffffff 347 * 348 * As such, go through the NUMA nodes one by one and fill out 349 * @bank_ptr[] starting from the end. When NUMA nodes are not present 350 * there is only one memory bank and none of the above matters. 351 */ 352 last = num_banks - 1; 353 for (i = 0; i < num_banks; i++) { 354 plat_get_memory_node(i, &bank_ptr[last]); 355 checksum += bank_ptr[last].base + bank_ptr[last].size; 356 last--; 357 } 358 359 /* Checksum must be 0 */ 360 manifest->plat_dram.checksum = ~checksum + 1UL; 361 362 /* Calculate the checksum of the plat_consoles structure */ 363 checksum = num_consoles + (uint64_t)console_ptr; 364 365 /* Zero out the console info struct */ 366 memset((void *)console_ptr, 0, sizeof(struct console_info) * num_consoles); 367 368 console_ptr[0].map_pages = 1; 369 console_ptr[0].base = PLAT_QEMU_BOOT_UART_BASE; 370 console_ptr[0].clk_in_hz = PLAT_QEMU_BOOT_UART_CLK_IN_HZ; 371 console_ptr[0].baud_rate = PLAT_QEMU_CONSOLE_BAUDRATE; 372 373 strlcpy(console_ptr[0].name, "pl011", sizeof(console_ptr[0].name)); 374 375 /* Update checksum */ 376 checksum += console_ptr[0].base + console_ptr[0].map_pages + 377 console_ptr[0].clk_in_hz + console_ptr[0].baud_rate; 378 379 /* Checksum must be 0 */ 380 manifest->plat_console.checksum = ~checksum + 1UL; 381 382 return 0; 383 } 384 #endif /* ENABLE_RME */ 385 386 /** 387 * plat_qemu_dt_runtime_address() - Get the final DT location in RAM 388 * 389 * When support is enabled on SBSA, the device tree is relocated from its 390 * original place at the beginning of the NS RAM to after the RMM. This 391 * function returns the address of the final location in RAM of the device 392 * tree. See function update_dt() in qemu_bl2_setup.c 393 * 394 * Return: The address of the final location in RAM of the device tree 395 */ 396 #if (ENABLE_RME && PLAT_qemu_sbsa) 397 void *plat_qemu_dt_runtime_address(void) 398 { 399 return (void *)(uintptr_t)PLAT_QEMU_DT_BASE; 400 } 401 #else 402 void *plat_qemu_dt_runtime_address(void) 403 { 404 return (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; 405 } 406 #endif /* (ENABLE_RME && PLAT_qemu_sbsa) */ 407