1*cc708597SJiafei Pan# 2*cc708597SJiafei Pan# Copyright 2022 NXP 3*cc708597SJiafei Pan# 4*cc708597SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 5*cc708597SJiafei Pan# 6*cc708597SJiafei Pan# 7*cc708597SJiafei Pan#------------------------------------------------------------------------------ 8*cc708597SJiafei Pan# 9*cc708597SJiafei Pan# This file contains the basic architecture definitions that drive the build 10*cc708597SJiafei Pan# 11*cc708597SJiafei Pan# ----------------------------------------------------------------------------- 12*cc708597SJiafei Pan 13*cc708597SJiafei PanCORE_TYPE := a72 14*cc708597SJiafei Pan 15*cc708597SJiafei PanCACHE_LINE := 6 16*cc708597SJiafei Pan 17*cc708597SJiafei Pan# set to GIC400 or GIC500 18*cc708597SJiafei PanGIC := GIC400 19*cc708597SJiafei Pan 20*cc708597SJiafei Pan# set to CCI400 or CCN504 or CCN508 21*cc708597SJiafei PanINTERCONNECT := CCI400 22*cc708597SJiafei Pan 23*cc708597SJiafei Pan# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24*cc708597SJiafei PanCHASSIS := 2 25*cc708597SJiafei Pan 26*cc708597SJiafei Pan# TZC IP Details TZC used is TZC380 or TZC400 27*cc708597SJiafei PanTZC_ID := TZC400 28*cc708597SJiafei Pan 29*cc708597SJiafei Pan# CONSOLE Details available is NS16550 or PL011 30*cc708597SJiafei PanCONSOLE := NS16550 31*cc708597SJiafei Pan 32*cc708597SJiafei Pan # Select the DDR PHY generation to be used 33*cc708597SJiafei PanPLAT_DDR_PHY := PHY_GEN1 34*cc708597SJiafei Pan 35*cc708597SJiafei PanPHYS_SYS := 64 36*cc708597SJiafei Pan 37*cc708597SJiafei Pan# ddr controller - set to MMDC or NXP 38*cc708597SJiafei PanDDRCNTLR := NXP 39*cc708597SJiafei Pan 40*cc708597SJiafei Pan# ddr phy - set to NXP or SNPS 41*cc708597SJiafei PanDDRPHY := NXP 42*cc708597SJiafei Pan 43*cc708597SJiafei Pan# Area of OCRAM reserved by ROM code 44*cc708597SJiafei PanNXP_ROM_RSVD := 0x5900 45*cc708597SJiafei Pan 46*cc708597SJiafei Pan# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 47*cc708597SJiafei Pan# Input to CST create_hdr_esbc tool 48*cc708597SJiafei PanCSF_HDR_SZ := 0x3000 49*cc708597SJiafei Pan 50*cc708597SJiafei Pan# In IMAGE_BL2, compile time flag for handling Cache coherency 51*cc708597SJiafei Pan# with CAAM for BL2 running from OCRAM 52*cc708597SJiafei PanSEC_MEM_NON_COHERENT := yes 53*cc708597SJiafei Pan 54*cc708597SJiafei Pan# OCRAM MAP 55*cc708597SJiafei PanOCRAM_START_ADDR := 0x10000000 56*cc708597SJiafei PanOCRAM_SIZE := 0x20000 57*cc708597SJiafei Pan 58*cc708597SJiafei Pan# BL2 binary is placed at start of OCRAM. 59*cc708597SJiafei Pan# Also used by create_pbl.mk. 60*cc708597SJiafei PanBL2_BASE := 0x10000000 61*cc708597SJiafei Pan 62*cc708597SJiafei Pan# After BL2 bin, OCRAM is used by ROM Code: 63*cc708597SJiafei Pan# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1) 64*cc708597SJiafei Pan 65*cc708597SJiafei Pan# After ROM Code, OCRAM is used by CSF header. 66*cc708597SJiafei Pan# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1) 67*cc708597SJiafei Pan 68*cc708597SJiafei Pan# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ) 69*cc708597SJiafei Pan# This value should be greater than BL2_TEXT_LIMIT 70*cc708597SJiafei Pan# Input to CST create_hdr_isbc tool 71*cc708597SJiafei PanBL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ)))) 72*cc708597SJiafei Pan# Covert to HEX to be used by create_pbl.mk 73*cc708597SJiafei PanBL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 74*cc708597SJiafei Pan 75*cc708597SJiafei Pan# Core Errata 76*cc708597SJiafei PanERRATA_A72_859971 := 1 77*cc708597SJiafei Pan 78*cc708597SJiafei Pan# SoC ERRATAS 79*cc708597SJiafei PanERRATA_SOC_A008850 := 1 80*cc708597SJiafei PanERRATA_SOC_A010539 := 1 81*cc708597SJiafei Pan 82*cc708597SJiafei Pan# DDR Errata 83*cc708597SJiafei PanERRATA_DDR_A008511 := 1 84*cc708597SJiafei PanERRATA_DDR_A009803 := 1 85*cc708597SJiafei PanERRATA_DDR_A009942 := 1 86*cc708597SJiafei PanERRATA_DDR_A010165 := 1 87*cc708597SJiafei Pan 88*cc708597SJiafei Pan# enable dynamic memory mapping 89*cc708597SJiafei PanPLAT_XLAT_TABLES_DYNAMIC := 1 90*cc708597SJiafei Pan 91*cc708597SJiafei Pan# Define Endianness of each module 92*cc708597SJiafei PanNXP_GUR_ENDIANNESS := BE 93*cc708597SJiafei PanNXP_DDR_ENDIANNESS := BE 94*cc708597SJiafei PanNXP_SEC_ENDIANNESS := BE 95*cc708597SJiafei PanNXP_SFP_ENDIANNESS := BE 96*cc708597SJiafei PanNXP_SNVS_ENDIANNESS := BE 97*cc708597SJiafei PanNXP_ESDHC_ENDIANNESS := BE 98*cc708597SJiafei PanNXP_QSPI_ENDIANNESS := BE 99*cc708597SJiafei PanNXP_FSPI_ENDIANNESS := BE 100*cc708597SJiafei PanNXP_SCFG_ENDIANNESS := BE 101*cc708597SJiafei PanNXP_GPIO_ENDIANNESS := BE 102*cc708597SJiafei PanNXP_IFC_ENDIANNESS := BE 103*cc708597SJiafei Pan 104*cc708597SJiafei PanNXP_SFP_VER := 3_2 105*cc708597SJiafei Pan 106*cc708597SJiafei Pan# OCRAM ECC Enabled 107*cc708597SJiafei PanOCRAM_ECC_EN := yes 108