1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <inttypes.h> 9 #include <stdint.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <assert.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/runtime_svc.h> 17 #include <errno.h> 18 #include <lib/mmio.h> 19 #include <lib/utils_def.h> 20 21 #include <memctrl.h> 22 #include <pmc.h> 23 #include <tegra_private.h> 24 #include <tegra_platform.h> 25 #include <tegra_def.h> 26 27 /******************************************************************************* 28 * PMC parameters 29 ******************************************************************************/ 30 #define PMC_READ U(0xaa) 31 #define PMC_WRITE U(0xbb) 32 33 /******************************************************************************* 34 * Tegra210 SiP SMCs 35 ******************************************************************************/ 36 #define TEGRA_SIP_PMC_COMMANDS U(0xC200FE00) 37 38 /******************************************************************************* 39 * This function is responsible for handling all T210 SiP calls 40 ******************************************************************************/ 41 int plat_sip_handler(uint32_t smc_fid, 42 uint64_t x1, 43 uint64_t x2, 44 uint64_t x3, 45 uint64_t x4, 46 const void *cookie, 47 void *handle, 48 uint64_t flags) 49 { 50 uint32_t val, ns; 51 52 /* Determine which security state this SMC originated from */ 53 ns = is_caller_non_secure(flags); 54 if (!ns) 55 SMC_RET1(handle, SMC_UNK); 56 57 if (smc_fid == TEGRA_SIP_PMC_COMMANDS) { 58 59 /* check the address is within PMC range and is 4byte aligned */ 60 if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) { 61 return -EINVAL; 62 } 63 64 switch (x2) { 65 /* Black listed PMC registers */ 66 case PMC_SCRATCH1: 67 case PMC_SCRATCH31 ... PMC_SCRATCH33: 68 case PMC_SCRATCH40: 69 case PMC_SCRATCH42: 70 case PMC_SCRATCH43 ... PMC_SCRATCH48: 71 case PMC_SCRATCH50 ... PMC_SCRATCH51: 72 case PMC_SCRATCH56 ... PMC_SCRATCH57: 73 /* PMC secure-only registers are not accessible */ 74 case PMC_DPD_ENABLE_0: 75 case PMC_FUSE_CONTROL_0: 76 case PMC_CRYPTO_OP_0: 77 case PMC_TSC_MULT_0: 78 case PMC_STICKY_BIT: 79 ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2); 80 return -EFAULT; 81 default: 82 /* Valid register */ 83 break; 84 } 85 86 /* Perform PMC read/write */ 87 if (x1 == PMC_READ) { 88 val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); 89 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val); 90 } else if (x1 == PMC_WRITE) { 91 mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); 92 } else { 93 return -EINVAL; 94 } 95 } else { 96 return -ENOTSUP; 97 } 98 return 0; 99 } 100