1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef T194_NVG_H 8 #define T194_NVG_H 9 10 /** 11 * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). 12 * Official documentation for this interface is included as part 13 * of the T194 TRM. 14 */ 15 16 /** 17 * Current version - Major version increments may break backwards 18 * compatiblity and binary compatibility. Minor version increments 19 * occur when there is only new functionality. 20 */ 21 enum { 22 TEGRA_NVG_VERSION_MAJOR = U(6), 23 TEGRA_NVG_VERSION_MINOR = U(6) 24 }; 25 26 typedef enum { 27 TEGRA_NVG_CHANNEL_VERSION = U(0), 28 TEGRA_NVG_CHANNEL_POWER_PERF = U(1), 29 TEGRA_NVG_CHANNEL_POWER_MODES = U(2), 30 TEGRA_NVG_CHANNEL_WAKE_TIME = U(3), 31 TEGRA_NVG_CHANNEL_CSTATE_INFO = U(4), 32 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = U(5), 33 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = U(6), 34 TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = U(8), 35 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = U(10), 36 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = U(11), 37 TEGRA_NVG_CHANNEL_NUM_CORES = U(20), 38 TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = U(21), 39 TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = U(22), 40 TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = U(23), 41 TEGRA_NVG_CHANNEL_SHUTDOWN = U(42), 42 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = U(43), 43 TEGRA_NVG_CHANNEL_ONLINE_CORE = U(44), 44 TEGRA_NVG_CHANNEL_CC3_CTRL = U(45), 45 TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = U(49), 46 TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = U(50), 47 TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = U(53), 48 TEGRA_NVG_CHANNEL_SECURITY_CONFIG = U(54), 49 TEGRA_NVG_CHANNEL_DEBUG_CONFIG = U(55), 50 TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = U(56), 51 TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = U(57), 52 TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = U(58), 53 TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = U(59), 54 TEGRA_NVG_CHANNEL_DDA_MCF_ISO = U(60), 55 TEGRA_NVG_CHANNEL_DDA_MCF_SISO = U(61), 56 TEGRA_NVG_CHANNEL_DDA_MCF_NISO = U(62), 57 TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = U(63), 58 TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = U(64), 59 TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = U(65), 60 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = U(66), 61 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = U(67), 62 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = U(68), 63 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = U(69), 64 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = U(70), 65 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = U(71), 66 TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = U(72), 67 TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = U(73), 68 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = U(74), 69 TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = U(75), 70 TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = U(76), 71 TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77), 72 TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78), 73 TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79), 74 75 TEGRA_NVG_CHANNEL_LAST_INDEX 76 } tegra_nvg_channel_id_t; 77 78 typedef enum { 79 NVG_STAT_QUERY_SC7_ENTRIES = U(1), 80 NVG_STAT_QUERY_CC6_ENTRIES = U(6), 81 NVG_STAT_QUERY_CG7_ENTRIES = U(7), 82 NVG_STAT_QUERY_C6_ENTRIES = U(10), 83 NVG_STAT_QUERY_C7_ENTRIES = U(14), 84 NVG_STAT_QUERY_SC7_RESIDENCY_SUM = U(32), 85 NVG_STAT_QUERY_CC6_RESIDENCY_SUM = U(41), 86 NVG_STAT_QUERY_CG7_RESIDENCY_SUM = U(46), 87 NVG_STAT_QUERY_C6_RESIDENCY_SUM = U(51), 88 NVG_STAT_QUERY_C7_RESIDENCY_SUM = U(56), 89 NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = U(60), 90 NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = U(61), 91 NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = U(62), 92 NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = U(63), 93 NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = U(64), 94 NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = U(70), 95 NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = U(71), 96 NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = U(72), 97 NVG_STAT_QUERY_C6_EXIT_TIME_SUM = U(73), 98 NVG_STAT_QUERY_C7_EXIT_TIME_SUM = U(74), 99 NVG_STAT_QUERY_SC7_ENTRY_LAST = U(80), 100 NVG_STAT_QUERY_CC6_ENTRY_LAST = U(81), 101 NVG_STAT_QUERY_CG7_ENTRY_LAST = U(82), 102 NVG_STAT_QUERY_C6_ENTRY_LAST = U(83), 103 NVG_STAT_QUERY_C7_ENTRY_LAST = U(84), 104 NVG_STAT_QUERY_SC7_EXIT_LAST = U(90), 105 NVG_STAT_QUERY_CC6_EXIT_LAST = U(91), 106 NVG_STAT_QUERY_CG7_EXIT_LAST = U(92), 107 NVG_STAT_QUERY_C6_EXIT_LAST = U(93), 108 NVG_STAT_QUERY_C7_EXIT_LAST = U(94) 109 110 } tegra_nvg_stat_query_t; 111 112 typedef enum { 113 TEGRA_NVG_CORE_C0 = U(0), 114 TEGRA_NVG_CORE_C1 = U(1), 115 TEGRA_NVG_CORE_C6 = U(6), 116 TEGRA_NVG_CORE_C7 = U(7), 117 TEGRA_NVG_CORE_WARMRSTREQ = U(8) 118 } tegra_nvg_core_sleep_state_t; 119 120 typedef enum { 121 TEGRA_NVG_SHUTDOWN = U(0), 122 TEGRA_NVG_REBOOT = U(1) 123 } tegra_nvg_shutdown_reboot_state_t; 124 125 typedef enum { 126 TEGRA_NVG_CLUSTER_CC0 = U(0), 127 TEGRA_NVG_CLUSTER_AUTO_CC1 = U(1), 128 TEGRA_NVG_CLUSTER_CC6 = U(6) 129 } tegra_nvg_cluster_sleep_state_t; 130 131 typedef enum { 132 TEGRA_NVG_CG_CG0 = U(0), 133 TEGRA_NVG_CG_CG7 = U(7) 134 } tegra_nvg_cluster_group_sleep_state_t; 135 136 typedef enum { 137 TEGRA_NVG_SYSTEM_SC0 = U(0), 138 TEGRA_NVG_SYSTEM_SC7 = U(7), 139 TEGRA_NVG_SYSTEM_SC8 = U(8) 140 } tegra_nvg_system_sleep_state_t; 141 142 // --------------------------------------------------------------------------- 143 // NVG Data subformats 144 // --------------------------------------------------------------------------- 145 146 typedef union { 147 uint64_t flat; 148 struct nvg_version_channel_t { 149 uint32_t minor_version : U(32); 150 uint32_t major_version : U(32); 151 } bits; 152 } nvg_version_data_t; 153 154 typedef union { 155 uint64_t flat; 156 struct nvg_power_perf_channel_t { 157 uint32_t perf_per_watt : U(1); 158 uint32_t reserved_31_1 : U(31); 159 uint32_t reserved_63_32 : U(32); 160 } bits; 161 } nvg_power_perf_channel_t; 162 163 typedef union { 164 uint64_t flat; 165 struct nvg_power_modes_channel_t { 166 uint32_t low_battery : U(1); 167 uint32_t reserved_1_1 : U(1); 168 uint32_t battery_save : U(1); 169 uint32_t reserved_31_3 : U(29); 170 uint32_t reserved_63_32 : U(32); 171 } bits; 172 } nvg_power_modes_channel_t; 173 174 typedef union nvg_channel_1_data_u { 175 uint64_t flat; 176 struct nvg_channel_1_data_s { 177 uint32_t perf_per_watt_mode : U(1); 178 uint32_t reserved_31_1 : U(31); 179 uint32_t reserved_63_32 : U(32); 180 } bits; 181 } nvg_channel_1_data_t; 182 183 typedef union { 184 uint64_t flat; 185 struct nvg_ccplex_cache_control_channel_t { 186 uint32_t gpu_ways : U(5); 187 uint32_t reserved_7_5 : U(3); 188 uint32_t gpu_only_ways : U(5); 189 uint32_t reserved_31_13 : U(19); 190 uint32_t reserved_63_32 : U(32); 191 } bits; 192 } nvg_ccplex_cache_control_channel_t; 193 194 typedef union nvg_channel_2_data_u { 195 uint64_t flat; 196 struct nvg_channel_2_data_s { 197 uint32_t reserved_1_0 : U(2); 198 uint32_t battery_saver_mode : U(1); 199 uint32_t reserved_31_3 : U(29); 200 uint32_t reserved_63_32 : U(32); 201 } bits; 202 } nvg_channel_2_data_t; 203 204 typedef union { 205 uint64_t flat; 206 struct nvg_wake_time_channel_t { 207 uint32_t wake_time : U(32); 208 uint32_t reserved_63_32 : U(32); 209 } bits; 210 } nvg_wake_time_channel_t; 211 212 typedef union { 213 uint64_t flat; 214 struct nvg_cstate_info_channel_t { 215 uint32_t cluster_state : U(3); 216 uint32_t reserved_6_3 : U(4); 217 uint32_t update_cluster : U(1); 218 uint32_t cg_cstate : U(3); 219 uint32_t reserved_14_11 : U(4); 220 uint32_t update_cg : U(1); 221 uint32_t system_cstate : U(4); 222 uint32_t reserved_22_20 : U(3); 223 uint32_t update_system : U(1); 224 uint32_t reserved_30_24 : U(7); 225 uint32_t update_wake_mask : U(1); 226 union { 227 uint32_t flat : U(32); 228 struct { 229 uint32_t vfiq : U(1); 230 uint32_t virq : U(1); 231 uint32_t fiq : U(1); 232 uint32_t irq : U(1); 233 uint32_t serror : U(1); 234 uint32_t reserved_10_5 : U(6); 235 uint32_t fiqout : U(1); 236 uint32_t irqout : U(1); 237 uint32_t reserved_31_13 : U(19); 238 } carmel; 239 } wake_mask; 240 } bits; 241 } nvg_cstate_info_channel_t; 242 243 typedef union { 244 uint64_t flat; 245 struct nvg_lower_bound_channel_t { 246 uint32_t crossover_value : U(32); 247 uint32_t reserved_63_32 : U(32); 248 } bits; 249 } nvg_lower_bound_channel_t; 250 251 typedef union { 252 uint64_t flat; 253 struct nvg_cstate_stat_query_channel_t { 254 uint32_t unit_id : U(4); 255 uint32_t reserved_15_4 : U(12); 256 uint32_t stat_id : U(16); 257 uint32_t reserved_63_32 : U(32); 258 } bits; 259 } nvg_cstate_stat_query_channel_t; 260 261 typedef union { 262 uint64_t flat; 263 struct nvg_num_cores_channel_t { 264 uint32_t num_cores : U(4); 265 uint32_t reserved_31_4 : U(28); 266 uint32_t reserved_63_32 : U(32); 267 } bits; 268 } nvg_num_cores_channel_t; 269 270 typedef union { 271 uint64_t flat; 272 struct nvg_unique_logical_id_channel_t { 273 uint32_t unique_core_id : U(3); 274 uint32_t reserved_31_3 : U(29); 275 uint32_t reserved_63_32 : U(32); 276 } bits; 277 } nvg_unique_logical_id_channel_t; 278 279 typedef union { 280 uint64_t flat; 281 struct nvg_logical_to_physical_mappings_channel_t { 282 uint32_t lcore0_pcore_id : U(4); 283 uint32_t lcore1_pcore_id : U(4); 284 uint32_t lcore2_pcore_id : U(4); 285 uint32_t lcore3_pcore_id : U(4); 286 uint32_t lcore4_pcore_id : U(4); 287 uint32_t lcore5_pcore_id : U(4); 288 uint32_t lcore6_pcore_id : U(4); 289 uint32_t lcore7_pcore_id : U(4); 290 uint32_t reserved_63_32 : U(32); 291 } bits; 292 } nvg_logical_to_physical_mappings_channel_t; 293 294 typedef union { 295 uint64_t flat; 296 struct nvg_logical_to_mpidr_channel_write_t { 297 uint32_t lcore_id : U(3); 298 uint32_t reserved_31_3 : U(29); 299 uint32_t reserved_63_32 : U(32); 300 } write; 301 struct nvg_logical_to_mpidr_channel_read_t { 302 uint32_t mpidr : U(32); 303 uint32_t reserved_63_32 : U(32); 304 } read; 305 } nvg_logical_to_mpidr_channel_t; 306 307 typedef union { 308 uint64_t flat; 309 struct nvg_is_sc7_allowed_channel_t { 310 uint32_t is_sc7_allowed : U(1); 311 uint32_t reserved_31_1 : U(31); 312 uint32_t reserved_63_32 : U(32); 313 } bits; 314 } nvg_is_sc7_allowed_channel_t; 315 316 typedef union { 317 uint64_t flat; 318 struct nvg_core_online_channel_t { 319 uint32_t core_id : U(4); 320 uint32_t reserved_31_4 : U(28); 321 uint32_t reserved_63_32 : U(32); 322 } bits; 323 } nvg_core_online_channel_t; 324 325 typedef union { 326 uint64_t flat; 327 struct nvg_cc3_control_channel_t { 328 uint32_t freq_req : U(9); 329 uint32_t reserved_30_9 : U(22); 330 uint32_t enable : U(1); 331 uint32_t reserved_63_32 : U(32); 332 } bits; 333 } nvg_cc3_control_channel_t; 334 335 typedef enum { 336 TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = U(0), 337 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = U(1), 338 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = U(2), 339 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = U(3), 340 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = U(4), 341 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = U(5), 342 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = U(6), 343 TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = U(7), 344 TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = U(8), 345 TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = U(9), 346 TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = U(10), 347 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = U(11), 348 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = U(12), 349 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = U(13), 350 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = U(14), 351 TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = U(15), 352 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = U(16), 353 TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = U(17), 354 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = U(18), 355 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = U(19), 356 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = U(20), 357 TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = U(21), 358 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = U(22), 359 TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = U(23), 360 TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = U(24), 361 TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = U(25), 362 TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = U(26), 363 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = U(27), 364 TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = U(28), 365 TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = U(29), 366 TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = U(30), 367 TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = U(31), 368 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = U(32), 369 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = U(33), 370 TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = U(34), 371 TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = U(35), 372 TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX 373 } tegra_nvg_channel_update_gsc_gsc_enum_t; 374 375 typedef union { 376 uint64_t flat; 377 struct nvg_update_ccplex_gsc_channel_t { 378 uint32_t gsc_enum : U(16); 379 uint32_t reserved_31_16 : U(16); 380 uint32_t reserved_63_32 : U(32); 381 } bits; 382 } nvg_update_ccplex_gsc_channel_t; 383 384 typedef union { 385 uint64_t flat; 386 struct nvg_security_config_channel_t { 387 uint32_t strict_checking_enabled : U(1); 388 uint32_t strict_checking_locked : U(1); 389 uint32_t reserved_31_2 : U(30); 390 uint32_t reserved_63_32 : U(32); 391 } bits; 392 } nvg_security_config_t; 393 394 typedef union { 395 uint64_t flat; 396 struct nvg_shutdown_channel_t { 397 uint32_t reboot : U(1); 398 uint32_t reserved_31_1 : U(31); 399 uint32_t reserved_63_32 : U(32); 400 } bits; 401 } nvg_shutdown_t; 402 403 typedef union { 404 uint64_t flat; 405 struct nvg_debug_config_channel_t { 406 uint32_t enter_debug_state_on_mca : U(1); 407 uint32_t reserved_31_1 : U(31); 408 uint32_t reserved_63_32 : U(32); 409 } bits; 410 } nvg_debug_config_t; 411 412 typedef union { 413 uint64_t flat; 414 struct nvg_hsm_error_ctrl_channel_t { 415 uint32_t uncorr : U(1); 416 uint32_t corr : U(1); 417 uint32_t reserved_31_2 : U(30); 418 uint32_t reserved_63_32 : U(32); 419 } bits; 420 } nvg_hsm_error_ctrl_channel_t; 421 422 extern nvg_debug_config_t nvg_debug_config; 423 424 #endif /* T194_NVG_H */ 425