1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef T194_NVG_H 8 #define T194_NVG_H 9 10 /** 11 * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). 12 * Official documentation for this interface is included as part 13 * of the T194 TRM. 14 */ 15 16 /** 17 * Current version - Major version increments may break backwards 18 * compatiblity and binary compatibility. Minor version increments 19 * occur when there is only new functionality. 20 */ 21 enum { 22 TEGRA_NVG_VERSION_MAJOR = 6, 23 TEGRA_NVG_VERSION_MINOR = 6 24 }; 25 26 typedef enum { 27 TEGRA_NVG_CHANNEL_VERSION = 0, 28 TEGRA_NVG_CHANNEL_POWER_PERF = 1, 29 TEGRA_NVG_CHANNEL_POWER_MODES = 2, 30 TEGRA_NVG_CHANNEL_WAKE_TIME = 3, 31 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, 32 TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, 33 TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, 34 TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, 35 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, 36 TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, 37 TEGRA_NVG_CHANNEL_NUM_CORES = 20, 38 TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = 21, 39 TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = 22, 40 TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = 23, 41 TEGRA_NVG_CHANNEL_SHUTDOWN = 42, 42 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, 43 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, 44 TEGRA_NVG_CHANNEL_CC3_CTRL = 45, 45 TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, 46 TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, 47 TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, 48 TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, 49 TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, 50 TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, 51 TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, 52 TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, 53 TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, 54 TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, 55 TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, 56 TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, 57 TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, 58 TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, 59 TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, 60 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, 61 TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, 62 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, 63 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, 64 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, 65 TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, 66 TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, 67 TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, 68 TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, 69 TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, 70 TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, 71 TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, 72 TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, 73 TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, 74 75 TEGRA_NVG_CHANNEL_LAST_INDEX 76 } tegra_nvg_channel_id_t; 77 78 typedef enum { 79 NVG_STAT_QUERY_SC7_ENTRIES = 1, 80 NVG_STAT_QUERY_CC6_ENTRIES = 6, 81 NVG_STAT_QUERY_CG7_ENTRIES = 7, 82 NVG_STAT_QUERY_C6_ENTRIES = 10, 83 NVG_STAT_QUERY_C7_ENTRIES = 14, 84 NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, 85 NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, 86 NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, 87 NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, 88 NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, 89 NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60, 90 NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61, 91 NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62, 92 NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63, 93 NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64, 94 NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70, 95 NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71, 96 NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72, 97 NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73, 98 NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74, 99 NVG_STAT_QUERY_SC7_ENTRY_LAST = 80, 100 NVG_STAT_QUERY_CC6_ENTRY_LAST = 81, 101 NVG_STAT_QUERY_CG7_ENTRY_LAST = 82, 102 NVG_STAT_QUERY_C6_ENTRY_LAST = 83, 103 NVG_STAT_QUERY_C7_ENTRY_LAST = 84, 104 NVG_STAT_QUERY_SC7_EXIT_LAST = 90, 105 NVG_STAT_QUERY_CC6_EXIT_LAST = 91, 106 NVG_STAT_QUERY_CG7_EXIT_LAST = 92, 107 NVG_STAT_QUERY_C6_EXIT_LAST = 93, 108 NVG_STAT_QUERY_C7_EXIT_LAST = 94 109 } tegra_nvg_stat_query_t; 110 111 typedef enum { 112 TEGRA_NVG_CORE_C0 = 0, 113 TEGRA_NVG_CORE_C1 = 1, 114 TEGRA_NVG_CORE_C6 = 6, 115 TEGRA_NVG_CORE_C7 = 7, 116 TEGRA_NVG_CORE_WARMRSTREQ = 8 117 } tegra_nvg_core_sleep_state_t; 118 119 typedef enum { 120 TEGRA_NVG_SHUTDOWN = 0U, 121 TEGRA_NVG_REBOOT = 1U 122 } tegra_nvg_shutdown_reboot_state_t; 123 124 typedef enum { 125 TEGRA_NVG_CLUSTER_CC0 = 0, 126 TEGRA_NVG_CLUSTER_AUTO_CC1 = 1, 127 TEGRA_NVG_CLUSTER_CC6 = 6 128 } tegra_nvg_cluster_sleep_state_t; 129 130 typedef enum { 131 TEGRA_NVG_CG_CG0 = 0, 132 TEGRA_NVG_CG_CG7 = 7 133 } tegra_nvg_cluster_group_sleep_state_t; 134 135 typedef enum { 136 TEGRA_NVG_SYSTEM_SC0 = 0, 137 TEGRA_NVG_SYSTEM_SC7 = 7, 138 TEGRA_NVG_SYSTEM_SC8 = 8 139 } tegra_nvg_system_sleep_state_t; 140 141 // --------------------------------------------------------------------------- 142 // NVG Data subformats 143 // --------------------------------------------------------------------------- 144 145 typedef union { 146 uint64_t flat; 147 struct nvg_version_channel_t { 148 uint32_t minor_version : 32; 149 uint32_t major_version : 32; 150 } bits; 151 } nvg_version_data_t; 152 153 typedef union { 154 uint64_t flat; 155 struct nvg_power_perf_channel_t { 156 uint32_t perf_per_watt : 1; 157 uint32_t reserved_31_1 : 31; 158 uint32_t reserved_63_32 : 32; 159 } bits; 160 } nvg_power_perf_channel_t; 161 162 typedef union { 163 uint64_t flat; 164 struct nvg_power_modes_channel_t { 165 uint32_t low_battery : 1; 166 uint32_t reserved_1_1 : 1; 167 uint32_t battery_save : 1; 168 uint32_t reserved_31_3 : 29; 169 uint32_t reserved_63_32 : 32; 170 } bits; 171 } nvg_power_modes_channel_t; 172 173 typedef union nvg_channel_1_data_u { 174 uint64_t flat; 175 struct nvg_channel_1_data_s { 176 uint32_t perf_per_watt_mode : 1; 177 uint32_t reserved_31_1 : 31; 178 uint32_t reserved_63_32 : 32; 179 } bits; 180 } nvg_channel_1_data_t; 181 182 typedef union { 183 uint64_t flat; 184 struct nvg_ccplex_cache_control_channel_t { 185 uint32_t gpu_ways : 5; 186 uint32_t reserved_7_5 : 3; 187 uint32_t gpu_only_ways : 5; 188 uint32_t reserved_31_13 : 19; 189 uint32_t reserved_63_32 : 32; 190 } bits; 191 } nvg_ccplex_cache_control_channel_t; 192 193 typedef union nvg_channel_2_data_u { 194 uint64_t flat; 195 struct nvg_channel_2_data_s { 196 uint32_t reserved_1_0 : 2; 197 uint32_t battery_saver_mode : 1; 198 uint32_t reserved_31_3 : 29; 199 uint32_t reserved_63_32 : 32; 200 } bits; 201 } nvg_channel_2_data_t; 202 203 typedef union { 204 uint64_t flat; 205 struct nvg_wake_time_channel_t { 206 uint32_t wake_time : 32; 207 uint32_t reserved_63_32 : 32; 208 } bits; 209 } nvg_wake_time_channel_t; 210 211 typedef union { 212 uint64_t flat; 213 struct nvg_cstate_info_channel_t { 214 uint32_t cluster_state : 3; 215 uint32_t reserved_6_3 : 4; 216 uint32_t update_cluster : 1; 217 uint32_t cg_cstate : 3; 218 uint32_t reserved_14_11 : 4; 219 uint32_t update_cg : 1; 220 uint32_t system_cstate : 4; 221 uint32_t reserved_22_20 : 3; 222 uint32_t update_system : 1; 223 uint32_t reserved_30_24 : 7; 224 uint32_t update_wake_mask : 1; 225 union { 226 uint32_t flat : 32; 227 struct { 228 uint32_t vfiq : 1; 229 uint32_t virq : 1; 230 uint32_t fiq : 1; 231 uint32_t irq : 1; 232 uint32_t serror : 1; 233 uint32_t reserved_10_5 : 6; 234 uint32_t fiqout : 1; 235 uint32_t irqout : 1; 236 uint32_t reserved_31_13 : 19; 237 } carmel; 238 } wake_mask; 239 } bits; 240 } nvg_cstate_info_channel_t; 241 242 typedef union { 243 uint64_t flat; 244 struct nvg_lower_bound_channel_t { 245 uint32_t crossover_value : 32; 246 uint32_t reserved_63_32 : 32; 247 } bits; 248 } nvg_lower_bound_channel_t; 249 250 typedef union { 251 uint64_t flat; 252 struct nvg_cstate_stat_query_channel_t { 253 uint32_t unit_id : 4; 254 uint32_t reserved_15_4 : 12; 255 uint32_t stat_id : 16; 256 uint32_t reserved_63_32 : 32; 257 } bits; 258 } nvg_cstate_stat_query_channel_t; 259 260 typedef union { 261 uint64_t flat; 262 struct nvg_num_cores_channel_t { 263 uint32_t num_cores : 4; 264 uint32_t reserved_31_4 : 28; 265 uint32_t reserved_63_32 : 32; 266 } bits; 267 } nvg_num_cores_channel_t; 268 269 typedef union { 270 uint64_t flat; 271 struct nvg_unique_logical_id_channel_t { 272 uint32_t unique_core_id : 3; 273 uint32_t reserved_31_3 : 29; 274 uint32_t reserved_63_32 : 32; 275 } bits; 276 } nvg_unique_logical_id_channel_t; 277 278 typedef union { 279 uint64_t flat; 280 struct nvg_logical_to_physical_mappings_channel_t { 281 uint32_t lcore0_pcore_id : 4; 282 uint32_t lcore1_pcore_id : 4; 283 uint32_t lcore2_pcore_id : 4; 284 uint32_t lcore3_pcore_id : 4; 285 uint32_t lcore4_pcore_id : 4; 286 uint32_t lcore5_pcore_id : 4; 287 uint32_t lcore6_pcore_id : 4; 288 uint32_t lcore7_pcore_id : 4; 289 uint32_t reserved_63_32 : 32; 290 } bits; 291 } nvg_logical_to_physical_mappings_channel_t; 292 293 typedef union { 294 uint64_t flat; 295 struct nvg_logical_to_mpidr_channel_write_t { 296 uint32_t lcore_id : 3; 297 uint32_t reserved_31_3 : 29; 298 uint32_t reserved_63_32 : 32; 299 } write; 300 struct nvg_logical_to_mpidr_channel_read_t { 301 uint32_t mpidr : 32; 302 uint32_t reserved_63_32 : 32; 303 } read; 304 } nvg_logical_to_mpidr_channel_t; 305 306 typedef union { 307 uint64_t flat; 308 struct nvg_is_sc7_allowed_channel_t { 309 uint32_t is_sc7_allowed : 1; 310 uint32_t reserved_31_1 : 31; 311 uint32_t reserved_63_32 : 32; 312 } bits; 313 } nvg_is_sc7_allowed_channel_t; 314 315 typedef union { 316 uint64_t flat; 317 struct nvg_core_online_channel_t { 318 uint32_t core_id : 4; 319 uint32_t reserved_31_4 : 28; 320 uint32_t reserved_63_32 : 32; 321 } bits; 322 } nvg_core_online_channel_t; 323 324 typedef union { 325 uint64_t flat; 326 struct nvg_cc3_control_channel_t { 327 uint32_t freq_req : 9; 328 uint32_t reserved_30_9 : 22; 329 uint32_t enable : 1; 330 uint32_t reserved_63_32 : 32; 331 } bits; 332 } nvg_cc3_control_channel_t; 333 334 typedef enum { 335 TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, 336 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, 337 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, 338 TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, 339 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, 340 TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, 341 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, 342 TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, 343 TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, 344 TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, 345 TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, 346 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, 347 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, 348 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, 349 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, 350 TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, 351 TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, 352 TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, 353 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, 354 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, 355 TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, 356 TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, 357 TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, 358 TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, 359 TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, 360 TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, 361 TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, 362 TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, 363 TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, 364 TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, 365 TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, 366 TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, 367 TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, 368 TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, 369 TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, 370 TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, 371 TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX 372 } tegra_nvg_channel_update_gsc_gsc_enum_t; 373 374 typedef union { 375 uint64_t flat; 376 struct nvg_update_ccplex_gsc_channel_t { 377 uint32_t gsc_enum : 16; 378 uint32_t reserved_31_16 : 16; 379 uint32_t reserved_63_32 : 32; 380 } bits; 381 } nvg_update_ccplex_gsc_channel_t; 382 383 typedef union { 384 uint64_t flat; 385 struct nvg_security_config_channel_t { 386 uint32_t strict_checking_enabled : 1; 387 uint32_t strict_checking_locked : 1; 388 uint32_t reserved_31_2 : 30; 389 uint32_t reserved_63_32 : 32; 390 } bits; 391 } nvg_security_config_t; 392 393 typedef union { 394 uint64_t flat; 395 struct nvg_shutdown_channel_t { 396 uint32_t reboot : 1; 397 uint32_t reserved_31_1 : 31; 398 uint32_t reserved_63_32 : 32; 399 } bits; 400 } nvg_shutdown_t; 401 402 typedef union { 403 uint64_t flat; 404 struct nvg_debug_config_channel_t { 405 uint32_t enter_debug_state_on_mca : 1; 406 uint32_t reserved_31_1 : 31; 407 uint32_t reserved_63_32 : 32; 408 } bits; 409 } nvg_debug_config_t; 410 411 typedef union { 412 uint64_t flat; 413 struct nvg_hsm_error_ctrl_channel_t { 414 uint32_t uncorr : 1; 415 uint32_t corr : 1; 416 uint32_t reserved_31_2 : 30; 417 uint32_t reserved_63_32 : 32; 418 } bits; 419 } nvg_hsm_error_ctrl_channel_t; 420 421 extern nvg_debug_config_t nvg_debug_config; 422 423 #endif 424 425