1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __MCE_PRIVATE_H__ 8 #define __MCE_PRIVATE_H__ 9 10 #include <tegra_def.h> 11 12 /******************************************************************************* 13 * Macros to prepare CSTATE info request 14 ******************************************************************************/ 15 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 16 #define CLUSTER_CSTATE_MASK 0x7U 17 #define CLUSTER_CSTATE_SHIFT 0X0U 18 #define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) 19 #define CCPLEX_CSTATE_MASK 0x7U 20 #define CCPLEX_CSTATE_SHIFT 8U 21 #define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) 22 #define SYSTEM_CSTATE_MASK 0xFU 23 #define SYSTEM_CSTATE_SHIFT 16U 24 #define SYSTEM_CSTATE_UPDATE_BIT (1U << 23) 25 #define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31) 26 #define CSTATE_WAKE_MASK_SHIFT 32U 27 #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU 28 29 /******************************************************************************* 30 * Core ID mask (bits 3:0 in the online request) 31 ******************************************************************************/ 32 #define MCE_CORE_ID_MASK 0xFU 33 34 /******************************************************************************* 35 * C-state statistics macros 36 ******************************************************************************/ 37 #define MCE_STAT_ID_SHIFT 16U 38 39 /******************************************************************************* 40 * Security config macros 41 ******************************************************************************/ 42 #define STRICT_CHECKING_ENABLED_SET (1UL << 0) 43 #define STRICT_CHECKING_LOCKED_SET (1UL << 1) 44 45 /* declarations for NVG handler functions */ 46 uint64_t nvg_get_version(void); 47 int32_t nvg_enable_power_perf_mode(void); 48 int32_t nvg_disable_power_perf_mode(void); 49 int32_t nvg_enable_power_saver_modes(void); 50 int32_t nvg_disable_power_saver_modes(void); 51 void nvg_set_wake_time(uint32_t wake_time); 52 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 53 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); 54 int32_t nvg_set_cstate_stat_query_value(uint64_t data); 55 uint64_t nvg_get_cstate_stat_query_value(void); 56 int32_t nvg_is_sc7_allowed(void); 57 int32_t nvg_online_core(uint32_t core); 58 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); 59 int32_t nvg_roc_clean_cache(void); 60 int32_t nvg_roc_flush_cache(void); 61 int32_t nvg_roc_clean_cache_trbits(void); 62 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); 63 void nvg_set_request_data(uint64_t req, uint64_t data); 64 void nvg_set_request(uint64_t req); 65 uint64_t nvg_get_result(void); 66 uint64_t nvg_cache_clean(void); 67 uint64_t nvg_cache_clean_inval(void); 68 uint64_t nvg_cache_inval_all(void); 69 int32_t nvg_roc_clean_cache_trbits(void); 70 void nvg_enable_strict_checking_mode(void); 71 72 /* MCE helper functions */ 73 void mce_enable_strict_checking(void); 74 75 #endif /* __MCE_PRIVATE_H__ */ 76