1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context_mgmt.h> 36 #include <debug.h> 37 #include <errno.h> 38 #include <mce.h> 39 #include <memctrl.h> 40 #include <runtime_svc.h> 41 #include <t18x_ari.h> 42 #include <tegra_private.h> 43 44 /******************************************************************************* 45 * Tegra186 SiP SMCs 46 ******************************************************************************/ 47 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 48 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00 49 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01 50 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02 51 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03 52 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04 53 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05 54 #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06 55 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07 56 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08 57 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09 58 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A 59 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B 60 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C 61 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D 62 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E 63 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F 64 65 /******************************************************************************* 66 * This function is responsible for handling all T186 SiP calls 67 ******************************************************************************/ 68 int plat_sip_handler(uint32_t smc_fid, 69 uint64_t x1, 70 uint64_t x2, 71 uint64_t x3, 72 uint64_t x4, 73 void *cookie, 74 void *handle, 75 uint64_t flags) 76 { 77 int mce_ret; 78 79 switch (smc_fid) { 80 81 /* 82 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 83 * 0x82FFFFFF SiP SMC space 84 */ 85 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 86 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 87 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 88 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 89 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 90 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 91 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 92 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 93 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 94 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 95 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 96 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 97 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 98 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 99 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 100 101 /* clean up the high bits */ 102 smc_fid &= MCE_CMD_MASK; 103 104 /* execute the command and store the result */ 105 mce_ret = mce_command_handler(smc_fid, x1, x2, x3); 106 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); 107 108 return 0; 109 110 case TEGRA_SIP_NEW_VIDEOMEM_REGION: 111 /* clean up the high bits */ 112 x1 = (uint32_t)x1; 113 x2 = (uint32_t)x2; 114 115 /* 116 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 117 * or falls outside of the valid DRAM range 118 */ 119 mce_ret = bl31_check_ns_address(x1, x2); 120 if (mce_ret) 121 return -ENOTSUP; 122 123 /* 124 * Check if Video Memory is aligned to 1MB. 125 */ 126 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 127 ERROR("Unaligned Video Memory base address!\n"); 128 return -ENOTSUP; 129 } 130 131 /* new video memory carveout settings */ 132 tegra_memctrl_videomem_setup(x1, x2); 133 134 return 0; 135 136 default: 137 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 138 break; 139 } 140 141 return -ENOTSUP; 142 } 143