1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/runtime_svc.h> 15 #include <denver.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 18 #include <mce.h> 19 #include <memctrl.h> 20 #include <t18x_ari.h> 21 #include <tegra_private.h> 22 23 /******************************************************************************* 24 * Offset to read the ref_clk counter value 25 ******************************************************************************/ 26 #define REF_CLK_OFFSET 4ULL 27 28 /******************************************************************************* 29 * Tegra186 SiP SMCs 30 ******************************************************************************/ 31 #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 32 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 33 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 34 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 35 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 36 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 37 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 38 39 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 40 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 41 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 42 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A 43 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B 44 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C 45 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D 46 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E 47 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F 48 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 49 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 50 #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 51 52 /******************************************************************************* 53 * This function is responsible for handling all T186 SiP calls 54 ******************************************************************************/ 55 int32_t plat_sip_handler(uint32_t smc_fid, 56 uint64_t x1, 57 uint64_t x2, 58 uint64_t x3, 59 uint64_t x4, 60 const void *cookie, 61 void *handle, 62 uint64_t flags) 63 { 64 int32_t mce_ret, ret = 0; 65 uint32_t impl, cpu; 66 uint32_t base, core_clk_ctr, ref_clk_ctr; 67 uint32_t local_smc_fid = smc_fid; 68 uint64_t local_x1 = x1, local_x2 = x2, local_x3 = x3; 69 70 (void)x4; 71 (void)cookie; 72 (void)flags; 73 74 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 75 /* 32-bit function, clear top parameter bits */ 76 77 local_x1 = (uint32_t)x1; 78 local_x2 = (uint32_t)x2; 79 local_x3 = (uint32_t)x3; 80 } 81 82 /* 83 * Convert SMC FID to SMC64, to support SMC32/SMC64 configurations 84 */ 85 local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); 86 87 switch (local_smc_fid) { 88 /* 89 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 90 * 0x82FFFFFF SiP SMC space 91 */ 92 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 93 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 94 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 95 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 96 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 97 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 98 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 99 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 100 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 101 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 102 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 103 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 104 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 105 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 106 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 107 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: 108 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: 109 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: 110 111 /* clean up the high bits */ 112 local_smc_fid &= MCE_CMD_MASK; 113 114 /* execute the command and store the result */ 115 mce_ret = mce_command_handler(local_smc_fid, local_x1, local_x2, local_x3); 116 write_ctx_reg(get_gpregs_ctx(handle), 117 CTX_GPREG_X0, (uint64_t)(mce_ret)); 118 break; 119 120 /* 121 * This function ID reads the Activity monitor's core/ref clock 122 * counter values for a core/cluster. 123 * 124 * x1 = MPIDR of the target core 125 * x2 = MIDR of the target core 126 */ 127 case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS: 128 129 cpu = (uint32_t)x1 & MPIDR_CPU_MASK; 130 impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 131 132 /* sanity check target CPU number */ 133 if (cpu > (uint32_t)PLATFORM_MAX_CPUS_PER_CLUSTER) { 134 ret = -EINVAL; 135 } else { 136 /* get the base address for the current CPU */ 137 base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE : 138 TEGRA_ARM_ACTMON_CTR_BASE; 139 140 /* read the clock counter values */ 141 core_clk_ctr = mmio_read_32(base + (8ULL * cpu)); 142 ref_clk_ctr = mmio_read_32(base + (8ULL * cpu) + REF_CLK_OFFSET); 143 144 /* return the counter values as two different parameters */ 145 write_ctx_reg(get_gpregs_ctx(handle), 146 CTX_GPREG_X1, (core_clk_ctr)); 147 write_ctx_reg(get_gpregs_ctx(handle), 148 CTX_GPREG_X2, (ref_clk_ctr)); 149 } 150 151 break; 152 153 default: 154 ret = -ENOTSUP; 155 break; 156 } 157 158 return ret; 159 } 160