1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MCE apertures used by the ARI interface 14 * 15 * Aperture 0 - Cpu0 (ARM Cortex A-57) 16 * Aperture 1 - Cpu1 (ARM Cortex A-57) 17 * Aperture 2 - Cpu2 (ARM Cortex A-57) 18 * Aperture 3 - Cpu3 (ARM Cortex A-57) 19 * Aperture 4 - Cpu4 (Denver15) 20 * Aperture 5 - Cpu5 (Denver15) 21 ******************************************************************************/ 22 #define MCE_ARI_APERTURE_0_OFFSET U(0x0) 23 #define MCE_ARI_APERTURE_1_OFFSET U(0x10000) 24 #define MCE_ARI_APERTURE_2_OFFSET U(0x20000) 25 #define MCE_ARI_APERTURE_3_OFFSET U(0x30000) 26 #define MCE_ARI_APERTURE_4_OFFSET U(0x40000) 27 #define MCE_ARI_APERTURE_5_OFFSET U(0x50000) 28 #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 29 30 /* number of apertures */ 31 #define MCE_ARI_APERTURES_MAX U(6) 32 33 /* each ARI aperture is 64KB */ 34 #define MCE_ARI_APERTURE_SIZE U(0x10000) 35 36 /******************************************************************************* 37 * CPU core id macros for the MCE_ONLINE_CORE ARI 38 ******************************************************************************/ 39 #define MCE_CORE_ID_MAX U(8) 40 #define MCE_CORE_ID_MASK U(0x7) 41 42 /******************************************************************************* 43 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 44 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 45 * parameter. 46 ******************************************************************************/ 47 #define PSTATE_ID_CORE_IDLE U(6) 48 #define PSTATE_ID_CORE_POWERDN U(7) 49 #define PSTATE_ID_SOC_POWERDN U(2) 50 51 /******************************************************************************* 52 * Platform power states (used by PSCI framework) 53 * 54 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 55 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 56 ******************************************************************************/ 57 #define PLAT_MAX_RET_STATE U(1) 58 #define PLAT_MAX_OFF_STATE U(8) 59 60 /******************************************************************************* 61 * Chip specific page table and MMU setup constants 62 ******************************************************************************/ 63 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 64 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 65 66 /******************************************************************************* 67 * Secure IRQ definitions 68 ******************************************************************************/ 69 #define TEGRA186_TOP_WDT_IRQ U(49) 70 #define TEGRA186_AON_WDT_IRQ U(50) 71 72 #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */ 73 74 /******************************************************************************* 75 * Tegra Miscellanous register constants 76 ******************************************************************************/ 77 #define TEGRA_MISC_BASE U(0x00100000) 78 #define HARDWARE_REVISION_OFFSET U(0x4) 79 80 #define MISCREG_PFCFG U(0x200C) 81 82 /******************************************************************************* 83 * Tegra TSA Controller constants 84 ******************************************************************************/ 85 #define TEGRA_TSA_BASE U(0x02400000) 86 87 /******************************************************************************* 88 * TSA configuration registers 89 ******************************************************************************/ 90 #define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010) 91 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100) 92 #define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038) 93 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100) 94 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010) 95 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100) 96 #define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008) 97 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100) 98 #define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008) 99 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100) 100 #define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018) 101 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100) 102 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018) 103 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100) 104 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028) 105 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100) 106 #define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018) 107 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100) 108 #define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008) 109 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100) 110 #define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018) 111 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100) 112 #define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028) 113 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100) 114 #define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038) 115 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100) 116 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008) 117 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100) 118 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018) 119 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100) 120 121 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) 122 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) 123 124 /******************************************************************************* 125 * Tegra General Purpose Centralised DMA constants 126 ******************************************************************************/ 127 #define TEGRA_GPCDMA_BASE ULL(0x2610000) 128 129 /******************************************************************************* 130 * Tegra Memory Controller constants 131 ******************************************************************************/ 132 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 133 #define TEGRA_MC_BASE U(0x02C10000) 134 135 /* General Security Carveout register macros */ 136 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 137 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 138 #define MC_GSC_ENABLE_TZ_LOCK_BIT (ULL(1) << 0) 139 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 140 #define MC_GSC_BASE_LO_SHIFT U(12) 141 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 142 #define MC_GSC_BASE_HI_SHIFT U(0) 143 #define MC_GSC_BASE_HI_MASK U(3) 144 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 145 146 /* TZDRAM carveout configuration registers */ 147 #define MC_SECURITY_CFG0_0 U(0x70) 148 #define MC_SECURITY_CFG1_0 U(0x74) 149 #define MC_SECURITY_CFG3_0 U(0x9BC) 150 151 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 152 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 153 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 154 155 /* Video Memory carveout configuration registers */ 156 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 157 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 158 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) 159 160 /* 161 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 162 * non-overlapping Video memory region 163 */ 164 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 165 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 166 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 167 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 168 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 169 170 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 171 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 172 #define MC_TZRAM_BASE_LO U(0x2194) 173 #define MC_TZRAM_BASE_HI U(0x2198) 174 #define MC_TZRAM_SIZE U(0x219C) 175 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 176 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 177 #define TZRAM_ALLOW_MPCORER (U(1) << 7) 178 #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 179 180 /******************************************************************************* 181 * Tegra UART Controller constants 182 ******************************************************************************/ 183 #define TEGRA_UARTA_BASE U(0x03100000) 184 #define TEGRA_UARTB_BASE U(0x03110000) 185 #define TEGRA_UARTC_BASE U(0x0C280000) 186 #define TEGRA_UARTD_BASE U(0x03130000) 187 #define TEGRA_UARTE_BASE U(0x03140000) 188 #define TEGRA_UARTF_BASE U(0x03150000) 189 #define TEGRA_UARTG_BASE U(0x0C290000) 190 191 /******************************************************************************* 192 * Tegra Fuse Controller related constants 193 ******************************************************************************/ 194 #define TEGRA_FUSE_BASE U(0x03820000) 195 #define OPT_SUBREVISION U(0x248) 196 #define SUBREVISION_MASK U(0xFF) 197 198 /******************************************************************************* 199 * GICv2 & interrupt handling related constants 200 ******************************************************************************/ 201 #define TEGRA_GICD_BASE U(0x03881000) 202 #define TEGRA_GICC_BASE U(0x03882000) 203 204 /******************************************************************************* 205 * Security Engine related constants 206 ******************************************************************************/ 207 #define TEGRA_SE0_BASE U(0x03AC0000) 208 #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 209 #define TEGRA_PKA1_BASE U(0x03AD0000) 210 #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) 211 #define TEGRA_RNG1_BASE U(0x03AE0000) 212 #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 213 214 /******************************************************************************* 215 * Tegra Clock and Reset Controller constants 216 ******************************************************************************/ 217 #define TEGRA_CAR_RESET_BASE U(0x05000000) 218 #define TEGRA_GPU_RESET_REG_OFFSET U(0x30) 219 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34) 220 #define GPU_RESET_BIT (U(1) << 0) 221 #define GPU_SET_BIT (U(1) << 0) 222 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) 223 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) 224 225 /******************************************************************************* 226 * Tegra micro-seconds timer constants 227 ******************************************************************************/ 228 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 229 #define TEGRA_TMRUS_SIZE U(0x1000) 230 231 /******************************************************************************* 232 * Tegra Power Mgmt Controller constants 233 ******************************************************************************/ 234 #define TEGRA_PMC_BASE U(0x0C360000) 235 236 /******************************************************************************* 237 * Tegra scratch registers constants 238 ******************************************************************************/ 239 #define TEGRA_SCRATCH_BASE U(0x0C390000) 240 #define SECURE_SCRATCH_RSV1_LO U(0x658) 241 #define SECURE_SCRATCH_RSV1_HI U(0x65C) 242 #define SECURE_SCRATCH_RSV6 U(0x680) 243 #define SECURE_SCRATCH_RSV11_LO U(0x6A8) 244 #define SECURE_SCRATCH_RSV11_HI U(0x6AC) 245 #define SECURE_SCRATCH_RSV53_LO U(0x7F8) 246 #define SECURE_SCRATCH_RSV53_HI U(0x7FC) 247 #define SECURE_SCRATCH_RSV55_LO U(0x808) 248 #define SECURE_SCRATCH_RSV55_HI U(0x80C) 249 250 #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO 251 #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI 252 #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6 253 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO 254 #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI 255 #define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO 256 #define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI 257 #define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO 258 #define SCRATCH_TZDRAM_ADDR_HI SECURE_SCRATCH_RSV55_HI 259 260 /******************************************************************************* 261 * Tegra Memory Mapped Control Register Access constants 262 ******************************************************************************/ 263 #define TEGRA_MMCRAB_BASE U(0x0E000000) 264 265 /******************************************************************************* 266 * Tegra Memory Mapped Activity Monitor Register Access constants 267 ******************************************************************************/ 268 #define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000) 269 #define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000) 270 271 /******************************************************************************* 272 * Tegra SMMU Controller constants 273 ******************************************************************************/ 274 #define TEGRA_SMMU0_BASE U(0x12000000) 275 276 /******************************************************************************* 277 * Tegra TZRAM constants 278 ******************************************************************************/ 279 #define TEGRA_TZRAM_BASE U(0x30000000) 280 #define TEGRA_TZRAM_SIZE U(0x40000) 281 282 #endif /* TEGRA_DEF_H */ 283