1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TEGRA_DEF_H__ 32 #define __TEGRA_DEF_H__ 33 34 #include <platform_def.h> 35 36 /******************************************************************************* 37 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 38 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 39 * parameter. 40 ******************************************************************************/ 41 #define PSTATE_ID_CORE_IDLE 6 42 #define PSTATE_ID_CORE_POWERDN 7 43 #define PSTATE_ID_SOC_POWERDN 2 44 45 /******************************************************************************* 46 * Platform power states (used by PSCI framework) 47 * 48 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 49 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 50 ******************************************************************************/ 51 #define PLAT_MAX_RET_STATE 1 52 #define PLAT_MAX_OFF_STATE 8 53 54 /******************************************************************************* 55 * Implementation defined ACTLR_EL3 bit definitions 56 ******************************************************************************/ 57 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 58 #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 59 #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 60 #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 61 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 62 #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 63 ACTLR_EL3_L2ECTLR_BIT | \ 64 ACTLR_EL3_L2CTLR_BIT | \ 65 ACTLR_EL3_CPUECTLR_BIT | \ 66 ACTLR_EL3_CPUACTLR_BIT) 67 68 /******************************************************************************* 69 * Secure IRQ definitions 70 ******************************************************************************/ 71 #define TEGRA186_TOP_WDT_IRQ 49 72 #define TEGRA186_AON_WDT_IRQ 50 73 74 #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 75 76 /******************************************************************************* 77 * Tegra Miscellanous register constants 78 ******************************************************************************/ 79 #define TEGRA_MISC_BASE 0x00100000 80 #define HARDWARE_REVISION_OFFSET 0x4 81 #define HARDWARE_MINOR_REVISION_MASK 0xf0000 82 #define HARDWARE_MINOR_REVISION_SHIFT 0x10 83 #define HARDWARE_REVISION_A01 1 84 85 /******************************************************************************* 86 * Tegra Memory Controller constants 87 ******************************************************************************/ 88 #define TEGRA_MC_STREAMID_BASE 0x02C00000 89 #define TEGRA_MC_BASE 0x02C10000 90 91 /******************************************************************************* 92 * Tegra UART Controller constants 93 ******************************************************************************/ 94 #define TEGRA_UARTA_BASE 0x03100000 95 #define TEGRA_UARTB_BASE 0x03110000 96 #define TEGRA_UARTC_BASE 0x0C280000 97 #define TEGRA_UARTD_BASE 0x03130000 98 #define TEGRA_UARTE_BASE 0x03140000 99 #define TEGRA_UARTF_BASE 0x03150000 100 #define TEGRA_UARTG_BASE 0x0C290000 101 102 /******************************************************************************* 103 * GICv2 & interrupt handling related constants 104 ******************************************************************************/ 105 #define TEGRA_GICD_BASE 0x03881000 106 #define TEGRA_GICC_BASE 0x03882000 107 108 /******************************************************************************* 109 * Tegra Clock and Reset Controller constants 110 ******************************************************************************/ 111 #define TEGRA_CAR_RESET_BASE 0x05000000 112 113 /******************************************************************************* 114 * Tegra micro-seconds timer constants 115 ******************************************************************************/ 116 #define TEGRA_TMRUS_BASE 0x0C2E0000 117 118 /******************************************************************************* 119 * Tegra Power Mgmt Controller constants 120 ******************************************************************************/ 121 #define TEGRA_PMC_BASE 0x0C360000 122 123 /******************************************************************************* 124 * Tegra scratch registers constants 125 ******************************************************************************/ 126 #define TEGRA_SCRATCH_BASE 0x0C390000 127 128 /******************************************************************************* 129 * Tegra Memory Mapped Control Register Access Bus constants 130 ******************************************************************************/ 131 #define TEGRA_MMCRAB_BASE 0x0E000000 132 133 /******************************************************************************* 134 * Tegra SMMU Controller constants 135 ******************************************************************************/ 136 #define TEGRA_SMMU_BASE 0x12000000 137 138 /******************************************************************************* 139 * Tegra TZRAM constants 140 ******************************************************************************/ 141 #define TEGRA_TZRAM_BASE 0x30000000 142 #define TEGRA_TZRAM_SIZE 0x50000 143 144 #endif /* __TEGRA_DEF_H__ */ 145