1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TEGRA_DEF_H 9 #define TEGRA_DEF_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MCE apertures used by the ARI interface 15 * 16 * Aperture 0 - Cpu0 (ARM Cortex A-57) 17 * Aperture 1 - Cpu1 (ARM Cortex A-57) 18 * Aperture 2 - Cpu2 (ARM Cortex A-57) 19 * Aperture 3 - Cpu3 (ARM Cortex A-57) 20 * Aperture 4 - Cpu4 (Denver15) 21 * Aperture 5 - Cpu5 (Denver15) 22 ******************************************************************************/ 23 #define MCE_ARI_APERTURE_0_OFFSET U(0x0) 24 #define MCE_ARI_APERTURE_1_OFFSET U(0x10000) 25 #define MCE_ARI_APERTURE_2_OFFSET U(0x20000) 26 #define MCE_ARI_APERTURE_3_OFFSET U(0x30000) 27 #define MCE_ARI_APERTURE_4_OFFSET U(0x40000) 28 #define MCE_ARI_APERTURE_5_OFFSET U(0x50000) 29 #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 30 31 /* number of apertures */ 32 #define MCE_ARI_APERTURES_MAX U(6) 33 34 /* each ARI aperture is 64KB */ 35 #define MCE_ARI_APERTURE_SIZE U(0x10000) 36 37 /******************************************************************************* 38 * CPU core id macros for the MCE_ONLINE_CORE ARI 39 ******************************************************************************/ 40 #define MCE_CORE_ID_MAX U(8) 41 #define MCE_CORE_ID_MASK U(0x7) 42 43 /******************************************************************************* 44 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 45 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 46 * parameter. 47 ******************************************************************************/ 48 #define PSTATE_ID_CORE_IDLE U(6) 49 #define PSTATE_ID_CORE_POWERDN U(7) 50 #define PSTATE_ID_SOC_POWERDN U(2) 51 52 /******************************************************************************* 53 * Platform power states (used by PSCI framework) 54 * 55 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 56 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 57 ******************************************************************************/ 58 #define PLAT_MAX_RET_STATE U(1) 59 #define PLAT_MAX_OFF_STATE U(8) 60 61 /******************************************************************************* 62 * Chip specific page table and MMU setup constants 63 ******************************************************************************/ 64 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 65 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 66 67 /******************************************************************************* 68 * Secure IRQ definitions 69 ******************************************************************************/ 70 #define TEGRA186_TOP_WDT_IRQ U(49) 71 #define TEGRA186_AON_WDT_IRQ U(50) 72 73 #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */ 74 75 /******************************************************************************* 76 * Clock identifier for the SE device 77 ******************************************************************************/ 78 #define TEGRA186_CLK_SE U(103) 79 #define TEGRA_CLK_SE TEGRA186_CLK_SE 80 81 /******************************************************************************* 82 * Tegra Miscellanous register constants 83 ******************************************************************************/ 84 #define TEGRA_MISC_BASE U(0x00100000) 85 #define HARDWARE_REVISION_OFFSET U(0x4) 86 87 #define MISCREG_PFCFG U(0x200C) 88 89 /******************************************************************************* 90 * Tegra TSA Controller constants 91 ******************************************************************************/ 92 #define TEGRA_TSA_BASE U(0x02400000) 93 94 /******************************************************************************* 95 * TSA configuration registers 96 ******************************************************************************/ 97 #define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010) 98 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100) 99 #define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038) 100 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100) 101 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010) 102 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100) 103 #define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008) 104 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100) 105 #define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008) 106 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100) 107 #define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018) 108 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100) 109 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018) 110 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100) 111 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028) 112 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100) 113 #define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018) 114 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100) 115 #define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008) 116 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100) 117 #define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018) 118 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100) 119 #define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028) 120 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100) 121 #define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038) 122 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100) 123 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008) 124 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100) 125 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018) 126 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100) 127 128 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) 129 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) 130 131 /******************************************************************************* 132 * Tegra General Purpose Centralised DMA constants 133 ******************************************************************************/ 134 #define TEGRA_GPCDMA_BASE ULL(0x2610000) 135 136 /******************************************************************************* 137 * Tegra Memory Controller constants 138 ******************************************************************************/ 139 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 140 #define TEGRA_MC_BASE U(0x02C10000) 141 142 /* General Security Carveout register macros */ 143 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 144 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 145 #define MC_GSC_ENABLE_TZ_LOCK_BIT (ULL(1) << 0) 146 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 147 #define MC_GSC_BASE_LO_SHIFT U(12) 148 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 149 #define MC_GSC_BASE_HI_SHIFT U(0) 150 #define MC_GSC_BASE_HI_MASK U(3) 151 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) 152 153 /* TZDRAM carveout configuration registers */ 154 #define MC_SECURITY_CFG0_0 U(0x70) 155 #define MC_SECURITY_CFG1_0 U(0x74) 156 #define MC_SECURITY_CFG3_0 U(0x9BC) 157 158 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) 159 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) 160 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) 161 162 /* Video Memory carveout configuration registers */ 163 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 164 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 165 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) 166 167 /* 168 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 169 * non-overlapping Video memory region 170 */ 171 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 172 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 173 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 174 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 175 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 176 177 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 178 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 179 #define MC_TZRAM_BASE_LO U(0x2194) 180 #define MC_TZRAM_BASE_HI U(0x2198) 181 #define MC_TZRAM_SIZE U(0x219C) 182 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) 183 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) 184 #define TZRAM_ALLOW_MPCORER (U(1) << 7) 185 #define TZRAM_ALLOW_MPCOREW (U(1) << 25) 186 187 /******************************************************************************* 188 * Tegra UART Controller constants 189 ******************************************************************************/ 190 #define TEGRA_UARTA_BASE U(0x03100000) 191 #define TEGRA_UARTB_BASE U(0x03110000) 192 #define TEGRA_UARTC_BASE U(0x0C280000) 193 #define TEGRA_UARTD_BASE U(0x03130000) 194 #define TEGRA_UARTE_BASE U(0x03140000) 195 #define TEGRA_UARTF_BASE U(0x03150000) 196 #define TEGRA_UARTG_BASE U(0x0C290000) 197 198 /******************************************************************************* 199 * Tegra Fuse Controller related constants 200 ******************************************************************************/ 201 #define TEGRA_FUSE_BASE U(0x03820000) 202 #define OPT_SUBREVISION U(0x248) 203 #define SUBREVISION_MASK U(0xFF) 204 205 /******************************************************************************* 206 * GICv2 & interrupt handling related constants 207 ******************************************************************************/ 208 #define TEGRA_GICD_BASE U(0x03881000) 209 #define TEGRA_GICC_BASE U(0x03882000) 210 211 /******************************************************************************* 212 * Security Engine related constants 213 ******************************************************************************/ 214 #define TEGRA_SE0_BASE U(0x03AC0000) 215 #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 216 #define TEGRA_PKA1_BASE U(0x03AD0000) 217 #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) 218 #define TEGRA_RNG1_BASE U(0x03AE0000) 219 #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 220 221 /******************************************************************************* 222 * Tegra HSP doorbell #0 constants 223 ******************************************************************************/ 224 #define TEGRA_HSP_DBELL_BASE U(0x03C90000) 225 #define HSP_DBELL_1_ENABLE U(0x104) 226 #define HSP_DBELL_3_TRIGGER U(0x300) 227 #define HSP_DBELL_3_ENABLE U(0x304) 228 229 /******************************************************************************* 230 * Tegra Clock and Reset Controller constants 231 ******************************************************************************/ 232 #define TEGRA_CAR_RESET_BASE U(0x05000000) 233 #define TEGRA_GPU_RESET_REG_OFFSET U(0x30) 234 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34) 235 #define GPU_RESET_BIT (U(1) << 0) 236 #define GPU_SET_BIT (U(1) << 0) 237 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) 238 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) 239 240 /******************************************************************************* 241 * Tegra micro-seconds timer constants 242 ******************************************************************************/ 243 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 244 #define TEGRA_TMRUS_SIZE U(0x1000) 245 246 /******************************************************************************* 247 * Tegra Power Mgmt Controller constants 248 ******************************************************************************/ 249 #define TEGRA_PMC_BASE U(0x0C360000) 250 251 /******************************************************************************* 252 * Tegra scratch registers constants 253 ******************************************************************************/ 254 #define TEGRA_SCRATCH_BASE U(0x0C390000) 255 #define SECURE_SCRATCH_RSV0_HI U(0x654) 256 #define SECURE_SCRATCH_RSV1_LO U(0x658) 257 #define SECURE_SCRATCH_RSV1_HI U(0x65C) 258 #define SECURE_SCRATCH_RSV6 U(0x680) 259 #define SECURE_SCRATCH_RSV11_LO U(0x6A8) 260 #define SECURE_SCRATCH_RSV11_HI U(0x6AC) 261 #define SECURE_SCRATCH_RSV53_LO U(0x7F8) 262 #define SECURE_SCRATCH_RSV53_HI U(0x7FC) 263 #define SECURE_SCRATCH_RSV55_LO U(0x808) 264 #define SECURE_SCRATCH_RSV55_HI U(0x80C) 265 #define SECURE_SCRATCH_RSV63_LO U(0x848) 266 #define SECURE_SCRATCH_RSV63_HI U(0x84C) 267 #define SECURE_SCRATCH_RSV64_LO U(0x850) 268 #define SECURE_SCRATCH_RSV64_HI U(0x854) 269 #define SECURE_SCRATCH_RSV65_LO U(0x858) 270 #define SECURE_SCRATCH_RSV65_HI U(0x85c) 271 #define SECURE_SCRATCH_RSV66_LO U(0x860) 272 #define SECURE_SCRATCH_RSV66_HI U(0x864) 273 #define SECURE_SCRATCH_RSV68_LO U(0x870) 274 275 #define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO 276 #define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI 277 #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6 278 #define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO 279 #define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI 280 #define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO 281 #define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI 282 #define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO 283 #define SCRATCH_TZDRAM_ADDR_HI SECURE_SCRATCH_RSV55_HI 284 285 /******************************************************************************* 286 * Tegra Memory Mapped Control Register Access constants 287 ******************************************************************************/ 288 #define TEGRA_MMCRAB_BASE U(0x0E000000) 289 290 /******************************************************************************* 291 * Tegra Memory Mapped Activity Monitor Register Access constants 292 ******************************************************************************/ 293 #define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000) 294 #define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000) 295 296 /******************************************************************************* 297 * Tegra SMMU Controller constants 298 ******************************************************************************/ 299 #define TEGRA_SMMU0_BASE U(0x12000000) 300 301 /******************************************************************************* 302 * Tegra TZRAM constants 303 ******************************************************************************/ 304 #define TEGRA_TZRAM_BASE U(0x30000000) 305 #define TEGRA_TZRAM_SIZE U(0x40000) 306 307 /******************************************************************************* 308 * Tegra CCPLEX-BPMP IPC constants 309 ******************************************************************************/ 310 #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x3004C000) 311 #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x3004D000) 312 #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ 313 314 /******************************************************************************* 315 * Tegra DRAM memory base address 316 ******************************************************************************/ 317 #define TEGRA_DRAM_BASE ULL(0x80000000) 318 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 319 320 #endif /* TEGRA_DEF_H */ 321