13cf3183fSVarun Wadekar /* 250cd8646SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 33cf3183fSVarun Wadekar * 43cf3183fSVarun Wadekar * Redistribution and use in source and binary forms, with or without 53cf3183fSVarun Wadekar * modification, are permitted provided that the following conditions are met: 63cf3183fSVarun Wadekar * 73cf3183fSVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83cf3183fSVarun Wadekar * list of conditions and the following disclaimer. 93cf3183fSVarun Wadekar * 103cf3183fSVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113cf3183fSVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123cf3183fSVarun Wadekar * and/or other materials provided with the distribution. 133cf3183fSVarun Wadekar * 143cf3183fSVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153cf3183fSVarun Wadekar * to endorse or promote products derived from this software without specific 163cf3183fSVarun Wadekar * prior written permission. 173cf3183fSVarun Wadekar * 183cf3183fSVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193cf3183fSVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203cf3183fSVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213cf3183fSVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223cf3183fSVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233cf3183fSVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243cf3183fSVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253cf3183fSVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263cf3183fSVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273cf3183fSVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283cf3183fSVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293cf3183fSVarun Wadekar */ 303cf3183fSVarun Wadekar 313cf3183fSVarun Wadekar #ifndef __TEGRA_DEF_H__ 323cf3183fSVarun Wadekar #define __TEGRA_DEF_H__ 333cf3183fSVarun Wadekar 343cf3183fSVarun Wadekar /******************************************************************************* 357afd4637SVarun Wadekar * These values are used by the PSCI implementation during the `CPU_SUSPEND` 367afd4637SVarun Wadekar * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 377afd4637SVarun Wadekar * parameter. 383cf3183fSVarun Wadekar ******************************************************************************/ 397afd4637SVarun Wadekar #define PSTATE_ID_CORE_IDLE 6 407afd4637SVarun Wadekar #define PSTATE_ID_CORE_POWERDN 7 417afd4637SVarun Wadekar #define PSTATE_ID_SOC_POWERDN 2 427afd4637SVarun Wadekar 437afd4637SVarun Wadekar /******************************************************************************* 447afd4637SVarun Wadekar * Platform power states (used by PSCI framework) 457afd4637SVarun Wadekar * 467afd4637SVarun Wadekar * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 477afd4637SVarun Wadekar * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 487afd4637SVarun Wadekar ******************************************************************************/ 497afd4637SVarun Wadekar #define PLAT_MAX_RET_STATE 1 507afd4637SVarun Wadekar #define PLAT_MAX_OFF_STATE 8 513cf3183fSVarun Wadekar 523cf3183fSVarun Wadekar /******************************************************************************* 533cf3183fSVarun Wadekar * Implementation defined ACTLR_EL3 bit definitions 543cf3183fSVarun Wadekar ******************************************************************************/ 553cf3183fSVarun Wadekar #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 563cf3183fSVarun Wadekar #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 573cf3183fSVarun Wadekar #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 583cf3183fSVarun Wadekar #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 593cf3183fSVarun Wadekar #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 603cf3183fSVarun Wadekar #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 613cf3183fSVarun Wadekar ACTLR_EL3_L2ECTLR_BIT | \ 623cf3183fSVarun Wadekar ACTLR_EL3_L2CTLR_BIT | \ 633cf3183fSVarun Wadekar ACTLR_EL3_CPUECTLR_BIT | \ 643cf3183fSVarun Wadekar ACTLR_EL3_CPUACTLR_BIT) 653cf3183fSVarun Wadekar 663cf3183fSVarun Wadekar /******************************************************************************* 6750cd8646SVarun Wadekar * Secure IRQ definitions 6850cd8646SVarun Wadekar ******************************************************************************/ 6950cd8646SVarun Wadekar #define TEGRA186_TOP_WDT_IRQ 49 7050cd8646SVarun Wadekar #define TEGRA186_AON_WDT_IRQ 50 7150cd8646SVarun Wadekar 7250cd8646SVarun Wadekar #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 7350cd8646SVarun Wadekar 7450cd8646SVarun Wadekar /******************************************************************************* 753cf3183fSVarun Wadekar * Tegra Miscellanous register constants 763cf3183fSVarun Wadekar ******************************************************************************/ 773cf3183fSVarun Wadekar #define TEGRA_MISC_BASE 0x00100000 78be87d920SVarun Wadekar #define HARDWARE_REVISION_OFFSET 0x4 79abd3a91dSVarun Wadekar 8050402b17SVarun Wadekar #define MISCREG_PFCFG 0x200C 813cf3183fSVarun Wadekar 823cf3183fSVarun Wadekar /******************************************************************************* 83e64ce3abSVarun Wadekar * Tegra TSA Controller constants 84e64ce3abSVarun Wadekar ******************************************************************************/ 85e64ce3abSVarun Wadekar #define TEGRA_TSA_BASE 0x02400000 86e64ce3abSVarun Wadekar 87e64ce3abSVarun Wadekar /******************************************************************************* 883cf3183fSVarun Wadekar * Tegra Memory Controller constants 893cf3183fSVarun Wadekar ******************************************************************************/ 903cf3183fSVarun Wadekar #define TEGRA_MC_STREAMID_BASE 0x02C00000 913cf3183fSVarun Wadekar #define TEGRA_MC_BASE 0x02C10000 923cf3183fSVarun Wadekar 933cf3183fSVarun Wadekar /******************************************************************************* 943cf3183fSVarun Wadekar * Tegra UART Controller constants 953cf3183fSVarun Wadekar ******************************************************************************/ 963cf3183fSVarun Wadekar #define TEGRA_UARTA_BASE 0x03100000 973cf3183fSVarun Wadekar #define TEGRA_UARTB_BASE 0x03110000 983cf3183fSVarun Wadekar #define TEGRA_UARTC_BASE 0x0C280000 993cf3183fSVarun Wadekar #define TEGRA_UARTD_BASE 0x03130000 1003cf3183fSVarun Wadekar #define TEGRA_UARTE_BASE 0x03140000 1013cf3183fSVarun Wadekar #define TEGRA_UARTF_BASE 0x03150000 1023cf3183fSVarun Wadekar #define TEGRA_UARTG_BASE 0x0C290000 1033cf3183fSVarun Wadekar 1043cf3183fSVarun Wadekar /******************************************************************************* 1051eed3838SVarun Wadekar * Tegra Fuse Controller related constants 1061eed3838SVarun Wadekar ******************************************************************************/ 1071eed3838SVarun Wadekar #define TEGRA_FUSE_BASE 0x03820000 1081eed3838SVarun Wadekar #define OPT_SUBREVISION 0x248 1091eed3838SVarun Wadekar #define SUBREVISION_MASK 0xFF 1101eed3838SVarun Wadekar 1111eed3838SVarun Wadekar /******************************************************************************* 1123cf3183fSVarun Wadekar * GICv2 & interrupt handling related constants 1133cf3183fSVarun Wadekar ******************************************************************************/ 1143cf3183fSVarun Wadekar #define TEGRA_GICD_BASE 0x03881000 1153cf3183fSVarun Wadekar #define TEGRA_GICC_BASE 0x03882000 1163cf3183fSVarun Wadekar 1173cf3183fSVarun Wadekar /******************************************************************************* 11850402b17SVarun Wadekar * Security Engine related constants 11950402b17SVarun Wadekar ******************************************************************************/ 12050402b17SVarun Wadekar #define TEGRA_SE0_BASE 0x03AC0000 12150402b17SVarun Wadekar #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 12250402b17SVarun Wadekar #define TEGRA_PKA1_BASE 0x03AD0000 12350402b17SVarun Wadekar #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 12450402b17SVarun Wadekar #define TEGRA_RNG1_BASE 0x03AE0000 12550402b17SVarun Wadekar #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 12650402b17SVarun Wadekar 12750402b17SVarun Wadekar /******************************************************************************* 1283cf3183fSVarun Wadekar * Tegra Clock and Reset Controller constants 1293cf3183fSVarun Wadekar ******************************************************************************/ 1303cf3183fSVarun Wadekar #define TEGRA_CAR_RESET_BASE 0x05000000 1313cf3183fSVarun Wadekar 1323cf3183fSVarun Wadekar /******************************************************************************* 1333cf3183fSVarun Wadekar * Tegra micro-seconds timer constants 1343cf3183fSVarun Wadekar ******************************************************************************/ 1353cf3183fSVarun Wadekar #define TEGRA_TMRUS_BASE 0x0C2E0000 1363cf3183fSVarun Wadekar 1373cf3183fSVarun Wadekar /******************************************************************************* 1383cf3183fSVarun Wadekar * Tegra Power Mgmt Controller constants 1393cf3183fSVarun Wadekar ******************************************************************************/ 1403cf3183fSVarun Wadekar #define TEGRA_PMC_BASE 0x0C360000 1413cf3183fSVarun Wadekar 1423cf3183fSVarun Wadekar /******************************************************************************* 1433cf3183fSVarun Wadekar * Tegra scratch registers constants 1443cf3183fSVarun Wadekar ******************************************************************************/ 1453cf3183fSVarun Wadekar #define TEGRA_SCRATCH_BASE 0x0C390000 14650402b17SVarun Wadekar #define SECURE_SCRATCH_RSV6 0x680 14750402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_LO 0x6A8 14850402b17SVarun Wadekar #define SECURE_SCRATCH_RSV11_HI 0x6AC 14948afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_LO 0x7F8 15048afb167SVarun Wadekar #define SECURE_SCRATCH_RSV53_HI 0x7FC 151*719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV54_HI 0x804 152*719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_LO 0x808 153*719f3ec2SHarvey Hsieh #define SECURE_SCRATCH_RSV55_HI 0x80C 1543cf3183fSVarun Wadekar 1553cf3183fSVarun Wadekar /******************************************************************************* 1563cf3183fSVarun Wadekar * Tegra Memory Mapped Control Register Access Bus constants 1573cf3183fSVarun Wadekar ******************************************************************************/ 1583cf3183fSVarun Wadekar #define TEGRA_MMCRAB_BASE 0x0E000000 1593cf3183fSVarun Wadekar 1603cf3183fSVarun Wadekar /******************************************************************************* 1613cf3183fSVarun Wadekar * Tegra SMMU Controller constants 1623cf3183fSVarun Wadekar ******************************************************************************/ 1633cf3183fSVarun Wadekar #define TEGRA_SMMU_BASE 0x12000000 1643cf3183fSVarun Wadekar 165d48c0c45SVarun Wadekar /******************************************************************************* 166d48c0c45SVarun Wadekar * Tegra TZRAM constants 167d48c0c45SVarun Wadekar ******************************************************************************/ 168d48c0c45SVarun Wadekar #define TEGRA_TZRAM_BASE 0x30000000 1692f583f8eSVarun Wadekar #define TEGRA_TZRAM_SIZE 0x40000 170d48c0c45SVarun Wadekar 1713cf3183fSVarun Wadekar #endif /* __TEGRA_DEF_H__ */ 172