1412dd5c5SVarun Wadekar /* 2*d48c0c45SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3412dd5c5SVarun Wadekar * 4412dd5c5SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5412dd5c5SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6412dd5c5SVarun Wadekar * 7412dd5c5SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8412dd5c5SVarun Wadekar * list of conditions and the following disclaimer. 9412dd5c5SVarun Wadekar * 10412dd5c5SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11412dd5c5SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12412dd5c5SVarun Wadekar * and/or other materials provided with the distribution. 13412dd5c5SVarun Wadekar * 14412dd5c5SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15412dd5c5SVarun Wadekar * to endorse or promote products derived from this software without specific 16412dd5c5SVarun Wadekar * prior written permission. 17412dd5c5SVarun Wadekar * 18412dd5c5SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19412dd5c5SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20412dd5c5SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21412dd5c5SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22412dd5c5SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23412dd5c5SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24412dd5c5SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25412dd5c5SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26412dd5c5SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27412dd5c5SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28412dd5c5SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29412dd5c5SVarun Wadekar */ 30412dd5c5SVarun Wadekar 31412dd5c5SVarun Wadekar #ifndef __MEMCTRLV2_H__ 32412dd5c5SVarun Wadekar #define __MEMCTRLV2_H__ 33412dd5c5SVarun Wadekar 34412dd5c5SVarun Wadekar #include <mmio.h> 35412dd5c5SVarun Wadekar #include <tegra_def.h> 36412dd5c5SVarun Wadekar 37412dd5c5SVarun Wadekar /******************************************************************************* 38412dd5c5SVarun Wadekar * StreamID to indicate no SMMU translations (requests to be steered on the 39412dd5c5SVarun Wadekar * SMMU bypass path) 40412dd5c5SVarun Wadekar ******************************************************************************/ 41412dd5c5SVarun Wadekar #define MC_STREAM_ID_MAX 0x7F 42412dd5c5SVarun Wadekar 43412dd5c5SVarun Wadekar /******************************************************************************* 44412dd5c5SVarun Wadekar * Stream ID Override Config registers 45412dd5c5SVarun Wadekar ******************************************************************************/ 46412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0 47412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70 48412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8 49412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0 50412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0 51412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8 52412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 53412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 54412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 55412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 56412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 57412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 58412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 59412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 60412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 61412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 62412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 63412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 64412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 65412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 66412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 67412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 68412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 69412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 70412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 71412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 72412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 73412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 74412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 75412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 76412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 77412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 78412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 79412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 80412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 81412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 82412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 83412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 84412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 85412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 86412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 87412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 88412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 89412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 90412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 91412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 92412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 93412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 94412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 95412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 96412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 97412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 98412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 99412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 100412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 101412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 102412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 103412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 104412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 105412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 106412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 107412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 108412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 109412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 110412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 111412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 112412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 113412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 114412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 115412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 116412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 117412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 118412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 119412dd5c5SVarun Wadekar 120412dd5c5SVarun Wadekar /******************************************************************************* 121412dd5c5SVarun Wadekar * Stream ID Security Config registers 122412dd5c5SVarun Wadekar ******************************************************************************/ 123412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_PTCR 0x4 124412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AFIR 0x74 125412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HDAR 0xAC 126412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4 127412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4 128412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SATAR 0xFC 129412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC 130412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C 131412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C 132412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AFIW 0x18C 133412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC 134412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC 135412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPRA 0x224 136412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPWA 0x234 137412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C 138412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254 139412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C 140412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264 141412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C 142412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4 143412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC 144412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4 145412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC 146412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304 147412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C 148412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314 149412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C 150412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324 151412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C 152412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334 153412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C 154412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSRD 0x364 155412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C 156412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VIW 0x394 157412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4 158412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC 159412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APER 0x3D4 160412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEW 0x3DC 161412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4 162412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC 163412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SESRD 0x404 164412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SESWR 0x40C 165412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ETRR 0x424 166412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ETRW 0x42C 167412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434 168412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C 169412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444 170412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C 171412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AXISR 0x464 172412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AXISW 0x46C 173412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_EQOSR 0x474 174412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C 175412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484 176412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C 177412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494 178412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C 179412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4 180412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC 181412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4 182412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONR 0x4BC 183412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONW 0x4C4 184412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC 185412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4 186412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCER 0x4DC 187412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4 188412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC 189412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4 190412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC 191412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504 192412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C 193412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514 194412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C 195412dd5c5SVarun Wadekar 196412dd5c5SVarun Wadekar /******************************************************************************* 197412dd5c5SVarun Wadekar * Memory Controller SMMU Bypass config register 198412dd5c5SVarun Wadekar ******************************************************************************/ 199412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG 0x1820 200412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CTRL_MASK 0x3 201412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CTRL_SHIFT 0 202412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 203412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 204412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 205412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 206412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 207412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 208412dd5c5SVarun Wadekar MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 209412dd5c5SVarun Wadekar 210412dd5c5SVarun Wadekar /******************************************************************************* 211412dd5c5SVarun Wadekar * Memory Controller SMMU Global Secure Aux. Configuration Register 212412dd5c5SVarun Wadekar ******************************************************************************/ 213412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_SECURE_ACR 0x10 214412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_SHIFT 16 215412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_4K (0 << ARM_SMMU_GSR0_PGSIZE_SHIFT) 216412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_64K (1 << ARM_SMMU_GSR0_PGSIZE_SHIFT) 217412dd5c5SVarun Wadekar 218412dd5c5SVarun Wadekar /******************************************************************************* 219412dd5c5SVarun Wadekar * Structure to hold the Stream ID to use to override client inputs 220412dd5c5SVarun Wadekar ******************************************************************************/ 221412dd5c5SVarun Wadekar typedef struct mc_streamid_override_cfg { 222412dd5c5SVarun Wadekar uint32_t offset; 223412dd5c5SVarun Wadekar uint8_t stream_id; 224412dd5c5SVarun Wadekar } mc_streamid_override_cfg_t; 225412dd5c5SVarun Wadekar 226412dd5c5SVarun Wadekar /******************************************************************************* 227412dd5c5SVarun Wadekar * Structure to hold the Stream ID Security Configuration settings 228412dd5c5SVarun Wadekar ******************************************************************************/ 229412dd5c5SVarun Wadekar typedef struct mc_streamid_security_cfg { 230412dd5c5SVarun Wadekar char *name; 231412dd5c5SVarun Wadekar uint32_t offset; 232412dd5c5SVarun Wadekar int override_enable; 233412dd5c5SVarun Wadekar int override_client_inputs; 234412dd5c5SVarun Wadekar int override_client_ns_flag; 235412dd5c5SVarun Wadekar } mc_streamid_security_cfg_t; 236412dd5c5SVarun Wadekar 237412dd5c5SVarun Wadekar #define OVERRIDE_DISABLE 1 238412dd5c5SVarun Wadekar #define OVERRIDE_ENABLE 0 239412dd5c5SVarun Wadekar #define CLIENT_FLAG_SECURE 0 240412dd5c5SVarun Wadekar #define CLIENT_FLAG_NON_SECURE 1 241412dd5c5SVarun Wadekar #define CLIENT_INPUTS_OVERRIDE 1 242412dd5c5SVarun Wadekar #define CLIENT_INPUTS_NO_OVERRIDE 0 243412dd5c5SVarun Wadekar 244412dd5c5SVarun Wadekar #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 245412dd5c5SVarun Wadekar { \ 246412dd5c5SVarun Wadekar .name = # off, \ 247412dd5c5SVarun Wadekar .offset = MC_STREAMID_SECURITY_CFG_ ## off, \ 248412dd5c5SVarun Wadekar .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 249412dd5c5SVarun Wadekar .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 250412dd5c5SVarun Wadekar .override_enable = OVERRIDE_ ## access \ 251412dd5c5SVarun Wadekar } 252412dd5c5SVarun Wadekar 253412dd5c5SVarun Wadekar /******************************************************************************* 254412dd5c5SVarun Wadekar * TZDRAM carveout configuration registers 255412dd5c5SVarun Wadekar ******************************************************************************/ 256412dd5c5SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 257412dd5c5SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 258412dd5c5SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 259412dd5c5SVarun Wadekar 260412dd5c5SVarun Wadekar /******************************************************************************* 261412dd5c5SVarun Wadekar * Video Memory carveout configuration registers 262412dd5c5SVarun Wadekar ******************************************************************************/ 263412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 264412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 265412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 266412dd5c5SVarun Wadekar 267*d48c0c45SVarun Wadekar /******************************************************************************* 268*d48c0c45SVarun Wadekar * TZRAM carveout configuration registers 269*d48c0c45SVarun Wadekar ******************************************************************************/ 270*d48c0c45SVarun Wadekar #define MC_TZRAM_BASE 0x1850 271*d48c0c45SVarun Wadekar #define MC_TZRAM_END 0x1854 272*d48c0c45SVarun Wadekar #define MC_TZRAM_HI_ADDR_BITS 0x1588 273*d48c0c45SVarun Wadekar #define TZRAM_ADDR_HI_BITS_MASK 0x3 274*d48c0c45SVarun Wadekar #define TZRAM_END_HI_BITS_SHIFT 8 275*d48c0c45SVarun Wadekar #define MC_TZRAM_REG_CTRL 0x185c 276*d48c0c45SVarun Wadekar #define DISABLE_TZRAM_ACCESS 1 277*d48c0c45SVarun Wadekar 278412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 279412dd5c5SVarun Wadekar { 280412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 281412dd5c5SVarun Wadekar } 282412dd5c5SVarun Wadekar 283412dd5c5SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 284412dd5c5SVarun Wadekar { 285412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 286412dd5c5SVarun Wadekar } 287412dd5c5SVarun Wadekar 288412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 289412dd5c5SVarun Wadekar { 290412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 291412dd5c5SVarun Wadekar } 292412dd5c5SVarun Wadekar 293412dd5c5SVarun Wadekar static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 294412dd5c5SVarun Wadekar { 295412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 296412dd5c5SVarun Wadekar } 297412dd5c5SVarun Wadekar 298412dd5c5SVarun Wadekar static inline uint32_t tegra_smmu_read_32(uint32_t off) 299412dd5c5SVarun Wadekar { 300412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_SMMU_BASE + off); 301412dd5c5SVarun Wadekar } 302412dd5c5SVarun Wadekar 303412dd5c5SVarun Wadekar static inline void tegra_smmu_write_32(uint32_t off, uint32_t val) 304412dd5c5SVarun Wadekar { 305412dd5c5SVarun Wadekar mmio_write_32(TEGRA_SMMU_BASE + off, val); 306412dd5c5SVarun Wadekar } 307412dd5c5SVarun Wadekar 308412dd5c5SVarun Wadekar #endif /* __MEMCTRLV2_H__ */ 309