1412dd5c5SVarun Wadekar /* 2*c959ea78SManish V Badarkhe * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 308e60f80SVarun Wadekar * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 4412dd5c5SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 6412dd5c5SVarun Wadekar */ 7412dd5c5SVarun Wadekar 8c3cf06f1SAntonio Nino Diaz #ifndef MEMCTRL_V2_H 9c3cf06f1SAntonio Nino Diaz #define MEMCTRL_V2_H 10412dd5c5SVarun Wadekar 1108e60f80SVarun Wadekar #include <arch.h> 1208e60f80SVarun Wadekar 13412dd5c5SVarun Wadekar #include <tegra_def.h> 14412dd5c5SVarun Wadekar 15ab2eb455SPuneet Saxena /******************************************************************************* 16ab2eb455SPuneet Saxena * Memory Controller SMMU Bypass config register 17ab2eb455SPuneet Saxena ******************************************************************************/ 18ab2eb455SPuneet Saxena #define MC_SMMU_BYPASS_CONFIG 0x1820U 19ab2eb455SPuneet Saxena #define MC_SMMU_BYPASS_CTRL_MASK 0x3U 20ab2eb455SPuneet Saxena #define MC_SMMU_BYPASS_CTRL_SHIFT 0U 21ab2eb455SPuneet Saxena #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT) 22ab2eb455SPuneet Saxena #define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT) 23ab2eb455SPuneet Saxena #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT) 24ab2eb455SPuneet Saxena #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT) 25ab2eb455SPuneet Saxena #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31) 26ab2eb455SPuneet Saxena #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 27ab2eb455SPuneet Saxena MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 28412dd5c5SVarun Wadekar 29*c959ea78SManish V Badarkhe #ifndef __ASSEMBLER__ 30412dd5c5SVarun Wadekar 312561cb50SAnthony Zhou #include <assert.h> 322561cb50SAnthony Zhou 33a391d494SPritesh Raithatha typedef struct mc_regs { 34a391d494SPritesh Raithatha uint32_t reg; 35a391d494SPritesh Raithatha uint32_t val; 36a391d494SPritesh Raithatha } mc_regs_t; 37a391d494SPritesh Raithatha 38a391d494SPritesh Raithatha #define mc_smmu_bypass_cfg \ 39a391d494SPritesh Raithatha { \ 40a391d494SPritesh Raithatha .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ 41a391d494SPritesh Raithatha .val = 0x00000000U, \ 42a391d494SPritesh Raithatha } 43a391d494SPritesh Raithatha 44a391d494SPritesh Raithatha #define _START_OF_TABLE_ \ 45a391d494SPritesh Raithatha { \ 46a391d494SPritesh Raithatha .reg = 0xCAFE05C7U, \ 47a391d494SPritesh Raithatha .val = 0x00000000U, \ 48a391d494SPritesh Raithatha } 49a391d494SPritesh Raithatha 50a391d494SPritesh Raithatha #define _END_OF_TABLE_ \ 51a391d494SPritesh Raithatha { \ 52a391d494SPritesh Raithatha .reg = 0xFFFFFFFFU, \ 53a391d494SPritesh Raithatha .val = 0xFFFFFFFFU, \ 54a391d494SPritesh Raithatha } 55a391d494SPritesh Raithatha 56*c959ea78SManish V Badarkhe #endif /* __ASSEMBLER__ */ 5708e60f80SVarun Wadekar 58*c959ea78SManish V Badarkhe #ifndef __ASSEMBLER__ 5908e60f80SVarun Wadekar 6008e60f80SVarun Wadekar #include <lib/mmio.h> 6106803cfdSPritesh Raithatha 62412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 63412dd5c5SVarun Wadekar { 64412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 65412dd5c5SVarun Wadekar } 66412dd5c5SVarun Wadekar 67412dd5c5SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 68412dd5c5SVarun Wadekar { 69412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 70412dd5c5SVarun Wadekar } 71412dd5c5SVarun Wadekar 7221ec61a9SVarun Wadekar #if defined(TEGRA_MC_STREAMID_BASE) 73412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 74412dd5c5SVarun Wadekar { 75412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 76412dd5c5SVarun Wadekar } 77412dd5c5SVarun Wadekar 78412dd5c5SVarun Wadekar static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 79412dd5c5SVarun Wadekar { 80412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 812561cb50SAnthony Zhou assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val); 82412dd5c5SVarun Wadekar } 8321ec61a9SVarun Wadekar #endif 84412dd5c5SVarun Wadekar 8508e60f80SVarun Wadekar void plat_memctrl_setup(void); 86e64ce3abSVarun Wadekar 8708e60f80SVarun Wadekar void plat_memctrl_restore(void); 8808e60f80SVarun Wadekar mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void); 8906803cfdSPritesh Raithatha 90d5bd0de6SVarun Wadekar /******************************************************************************* 91a391d494SPritesh Raithatha * Handler to save MC settings before "System Suspend" to TZDRAM 92a391d494SPritesh Raithatha * 93a391d494SPritesh Raithatha * Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl 94a391d494SPritesh Raithatha ******************************************************************************/ 95a391d494SPritesh Raithatha void tegra_mc_save_context(uint64_t mc_ctx_addr); 96a391d494SPritesh Raithatha 97a391d494SPritesh Raithatha /******************************************************************************* 98d5bd0de6SVarun Wadekar * Handler to program the scratch registers with TZDRAM settings for the 99d5bd0de6SVarun Wadekar * resume firmware. 100d5bd0de6SVarun Wadekar * 101d5bd0de6SVarun Wadekar * Implemented by SoCs under tegra/soc/txxx 102d5bd0de6SVarun Wadekar ******************************************************************************/ 103d5bd0de6SVarun Wadekar void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes); 104d5bd0de6SVarun Wadekar 105d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 106e64ce3abSVarun Wadekar 107c3cf06f1SAntonio Nino Diaz #endif /* MEMCTRL_V2_H */ 108