1412dd5c5SVarun Wadekar /* 2d48c0c45SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3412dd5c5SVarun Wadekar * 4412dd5c5SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5412dd5c5SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6412dd5c5SVarun Wadekar * 7412dd5c5SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8412dd5c5SVarun Wadekar * list of conditions and the following disclaimer. 9412dd5c5SVarun Wadekar * 10412dd5c5SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11412dd5c5SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12412dd5c5SVarun Wadekar * and/or other materials provided with the distribution. 13412dd5c5SVarun Wadekar * 14412dd5c5SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15412dd5c5SVarun Wadekar * to endorse or promote products derived from this software without specific 16412dd5c5SVarun Wadekar * prior written permission. 17412dd5c5SVarun Wadekar * 18412dd5c5SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19412dd5c5SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20412dd5c5SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21412dd5c5SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22412dd5c5SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23412dd5c5SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24412dd5c5SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25412dd5c5SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26412dd5c5SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27412dd5c5SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28412dd5c5SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29412dd5c5SVarun Wadekar */ 30412dd5c5SVarun Wadekar 31412dd5c5SVarun Wadekar #ifndef __MEMCTRLV2_H__ 32412dd5c5SVarun Wadekar #define __MEMCTRLV2_H__ 33412dd5c5SVarun Wadekar 34412dd5c5SVarun Wadekar #include <mmio.h> 35412dd5c5SVarun Wadekar #include <tegra_def.h> 36412dd5c5SVarun Wadekar 37412dd5c5SVarun Wadekar /******************************************************************************* 38412dd5c5SVarun Wadekar * StreamID to indicate no SMMU translations (requests to be steered on the 39412dd5c5SVarun Wadekar * SMMU bypass path) 40412dd5c5SVarun Wadekar ******************************************************************************/ 41412dd5c5SVarun Wadekar #define MC_STREAM_ID_MAX 0x7F 42412dd5c5SVarun Wadekar 43412dd5c5SVarun Wadekar /******************************************************************************* 44412dd5c5SVarun Wadekar * Stream ID Override Config registers 45412dd5c5SVarun Wadekar ******************************************************************************/ 46412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0 47412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70 48412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8 49412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0 50412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0 51412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8 52412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 53412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 54412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 55412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 56412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 57412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 58412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 59412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 60412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 61412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 62412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 63412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 64412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 65412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 66412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 67412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 68412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 69412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 70412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 71412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 72412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 73412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 74412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 75412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 76412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 77412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 78412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 79412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 80412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 81412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 82412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 83412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 84412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 85412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 86412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 87412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 88412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 89412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 90412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 91412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 92412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 93412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 94412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 95412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 96412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 97412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 98412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 99412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 100412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 101412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 102412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 103412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 104412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 105412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 106412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 107412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 108412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 109412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 110412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 111412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 112412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 113412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 114412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 115412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 116412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 117412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 118412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 119412dd5c5SVarun Wadekar 120412dd5c5SVarun Wadekar /******************************************************************************* 121412dd5c5SVarun Wadekar * Stream ID Security Config registers 122412dd5c5SVarun Wadekar ******************************************************************************/ 123412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_PTCR 0x4 124412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AFIR 0x74 125412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HDAR 0xAC 126412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4 127412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4 128412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SATAR 0xFC 129412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC 130412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C 131412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C 132412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AFIW 0x18C 133412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC 134412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC 135412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPRA 0x224 136412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPWA 0x234 137412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C 138412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254 139412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C 140412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264 141412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C 142412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4 143412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC 144412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4 145412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC 146412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304 147412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C 148412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314 149412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C 150412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324 151412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C 152412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334 153412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C 154412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSRD 0x364 155412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C 156412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VIW 0x394 157412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4 158412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC 159412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APER 0x3D4 160412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEW 0x3DC 161412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4 162412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC 163412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SESRD 0x404 164412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SESWR 0x40C 165412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ETRR 0x424 166412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ETRW 0x42C 167412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434 168412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C 169412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444 170412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C 171412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AXISR 0x464 172412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AXISW 0x46C 173412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_EQOSR 0x474 174412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C 175412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484 176412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C 177412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494 178412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C 179412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4 180412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC 181412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4 182412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONR 0x4BC 183412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONW 0x4C4 184412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC 185412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4 186412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCER 0x4DC 187412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4 188412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC 189412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4 190412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC 191412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504 192412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C 193412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514 194412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C 195412dd5c5SVarun Wadekar 196412dd5c5SVarun Wadekar /******************************************************************************* 197412dd5c5SVarun Wadekar * Memory Controller SMMU Bypass config register 198412dd5c5SVarun Wadekar ******************************************************************************/ 199412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG 0x1820 200412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CTRL_MASK 0x3 201412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CTRL_SHIFT 0 202412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 203412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 204412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 205412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 206412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 207412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 208412dd5c5SVarun Wadekar MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 209412dd5c5SVarun Wadekar 210412dd5c5SVarun Wadekar /******************************************************************************* 211*be87d920SVarun Wadekar * Memory Controller transaction override config registers 212*be87d920SVarun Wadekar ******************************************************************************/ 213*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 214*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 215*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 216*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 217*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 218*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 219*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 220*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328 221*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 222*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 223*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 224*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 225*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 226*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 227*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 228*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 229*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 230*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 231*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 232*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 233*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 234*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308 235*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 236*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 237*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 238*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 239*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 240*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 241*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 242*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 243*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 244*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 245*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 246*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 247*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 248*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 249*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 250*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 251*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 252*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 253*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 254*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 255*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 256*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 257*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 258*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 259*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 260*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 261*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 262*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 263*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 264*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 265*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 266*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 267*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 268*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 269*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 270*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 271*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 272*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 273*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070 274*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 275*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 276*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 277*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 278*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 279*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 280*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 281*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 282*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 283*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188 284*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 285*be87d920SVarun Wadekar 286*be87d920SVarun Wadekar /******************************************************************************* 287*be87d920SVarun Wadekar * Non-SO_DEV transactions override values for CGID_TAG bitfield for the 288*be87d920SVarun Wadekar * MC_TXN_OVERRIDE_CONFIG_{module} registers 289*be87d920SVarun Wadekar ******************************************************************************/ 290*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0 291*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1 292*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2 293*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3 294*be87d920SVarun Wadekar #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3 295*be87d920SVarun Wadekar 296*be87d920SVarun Wadekar /******************************************************************************* 297*be87d920SVarun Wadekar * Structure to hold the transaction override settings to use to override 298*be87d920SVarun Wadekar * client inputs 299*be87d920SVarun Wadekar ******************************************************************************/ 300*be87d920SVarun Wadekar typedef struct mc_txn_override_cfg { 301*be87d920SVarun Wadekar uint32_t offset; 302*be87d920SVarun Wadekar uint8_t cgid_tag; 303*be87d920SVarun Wadekar } mc_txn_override_cfg_t; 304*be87d920SVarun Wadekar 305*be87d920SVarun Wadekar #define mc_make_txn_override_cfg(off, val) \ 306*be87d920SVarun Wadekar { \ 307*be87d920SVarun Wadekar .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 308*be87d920SVarun Wadekar .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 309*be87d920SVarun Wadekar } 310*be87d920SVarun Wadekar 311*be87d920SVarun Wadekar /******************************************************************************* 312412dd5c5SVarun Wadekar * Memory Controller SMMU Global Secure Aux. Configuration Register 313412dd5c5SVarun Wadekar ******************************************************************************/ 314412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_SECURE_ACR 0x10 315412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_SHIFT 16 316412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_4K (0 << ARM_SMMU_GSR0_PGSIZE_SHIFT) 317412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_64K (1 << ARM_SMMU_GSR0_PGSIZE_SHIFT) 318412dd5c5SVarun Wadekar 319412dd5c5SVarun Wadekar /******************************************************************************* 320412dd5c5SVarun Wadekar * Structure to hold the Stream ID to use to override client inputs 321412dd5c5SVarun Wadekar ******************************************************************************/ 322412dd5c5SVarun Wadekar typedef struct mc_streamid_override_cfg { 323412dd5c5SVarun Wadekar uint32_t offset; 324412dd5c5SVarun Wadekar uint8_t stream_id; 325412dd5c5SVarun Wadekar } mc_streamid_override_cfg_t; 326412dd5c5SVarun Wadekar 327412dd5c5SVarun Wadekar /******************************************************************************* 328412dd5c5SVarun Wadekar * Structure to hold the Stream ID Security Configuration settings 329412dd5c5SVarun Wadekar ******************************************************************************/ 330412dd5c5SVarun Wadekar typedef struct mc_streamid_security_cfg { 331412dd5c5SVarun Wadekar char *name; 332412dd5c5SVarun Wadekar uint32_t offset; 333412dd5c5SVarun Wadekar int override_enable; 334412dd5c5SVarun Wadekar int override_client_inputs; 335412dd5c5SVarun Wadekar int override_client_ns_flag; 336412dd5c5SVarun Wadekar } mc_streamid_security_cfg_t; 337412dd5c5SVarun Wadekar 338412dd5c5SVarun Wadekar #define OVERRIDE_DISABLE 1 339412dd5c5SVarun Wadekar #define OVERRIDE_ENABLE 0 340412dd5c5SVarun Wadekar #define CLIENT_FLAG_SECURE 0 341412dd5c5SVarun Wadekar #define CLIENT_FLAG_NON_SECURE 1 342412dd5c5SVarun Wadekar #define CLIENT_INPUTS_OVERRIDE 1 343412dd5c5SVarun Wadekar #define CLIENT_INPUTS_NO_OVERRIDE 0 344412dd5c5SVarun Wadekar 345412dd5c5SVarun Wadekar #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 346412dd5c5SVarun Wadekar { \ 347412dd5c5SVarun Wadekar .name = # off, \ 348412dd5c5SVarun Wadekar .offset = MC_STREAMID_SECURITY_CFG_ ## off, \ 349412dd5c5SVarun Wadekar .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 350412dd5c5SVarun Wadekar .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 351412dd5c5SVarun Wadekar .override_enable = OVERRIDE_ ## access \ 352412dd5c5SVarun Wadekar } 353412dd5c5SVarun Wadekar 354412dd5c5SVarun Wadekar /******************************************************************************* 355412dd5c5SVarun Wadekar * TZDRAM carveout configuration registers 356412dd5c5SVarun Wadekar ******************************************************************************/ 357412dd5c5SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 358412dd5c5SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 359412dd5c5SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 360412dd5c5SVarun Wadekar 361412dd5c5SVarun Wadekar /******************************************************************************* 362412dd5c5SVarun Wadekar * Video Memory carveout configuration registers 363412dd5c5SVarun Wadekar ******************************************************************************/ 364412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 365412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 366412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 367412dd5c5SVarun Wadekar 368d48c0c45SVarun Wadekar /******************************************************************************* 369d48c0c45SVarun Wadekar * TZRAM carveout configuration registers 370d48c0c45SVarun Wadekar ******************************************************************************/ 371d48c0c45SVarun Wadekar #define MC_TZRAM_BASE 0x1850 372d48c0c45SVarun Wadekar #define MC_TZRAM_END 0x1854 373d48c0c45SVarun Wadekar #define MC_TZRAM_HI_ADDR_BITS 0x1588 374d48c0c45SVarun Wadekar #define TZRAM_ADDR_HI_BITS_MASK 0x3 375d48c0c45SVarun Wadekar #define TZRAM_END_HI_BITS_SHIFT 8 376d48c0c45SVarun Wadekar #define MC_TZRAM_REG_CTRL 0x185c 377d48c0c45SVarun Wadekar #define DISABLE_TZRAM_ACCESS 1 378d48c0c45SVarun Wadekar 379412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 380412dd5c5SVarun Wadekar { 381412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 382412dd5c5SVarun Wadekar } 383412dd5c5SVarun Wadekar 384412dd5c5SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 385412dd5c5SVarun Wadekar { 386412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 387412dd5c5SVarun Wadekar } 388412dd5c5SVarun Wadekar 389412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 390412dd5c5SVarun Wadekar { 391412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 392412dd5c5SVarun Wadekar } 393412dd5c5SVarun Wadekar 394412dd5c5SVarun Wadekar static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 395412dd5c5SVarun Wadekar { 396412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 397412dd5c5SVarun Wadekar } 398412dd5c5SVarun Wadekar 399412dd5c5SVarun Wadekar static inline uint32_t tegra_smmu_read_32(uint32_t off) 400412dd5c5SVarun Wadekar { 401412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_SMMU_BASE + off); 402412dd5c5SVarun Wadekar } 403412dd5c5SVarun Wadekar 404412dd5c5SVarun Wadekar static inline void tegra_smmu_write_32(uint32_t off, uint32_t val) 405412dd5c5SVarun Wadekar { 406412dd5c5SVarun Wadekar mmio_write_32(TEGRA_SMMU_BASE + off, val); 407412dd5c5SVarun Wadekar } 408412dd5c5SVarun Wadekar 409412dd5c5SVarun Wadekar #endif /* __MEMCTRLV2_H__ */ 410