1*412dd5c5SVarun Wadekar /* 2*412dd5c5SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*412dd5c5SVarun Wadekar * 4*412dd5c5SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*412dd5c5SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*412dd5c5SVarun Wadekar * 7*412dd5c5SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*412dd5c5SVarun Wadekar * list of conditions and the following disclaimer. 9*412dd5c5SVarun Wadekar * 10*412dd5c5SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*412dd5c5SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*412dd5c5SVarun Wadekar * and/or other materials provided with the distribution. 13*412dd5c5SVarun Wadekar * 14*412dd5c5SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*412dd5c5SVarun Wadekar * to endorse or promote products derived from this software without specific 16*412dd5c5SVarun Wadekar * prior written permission. 17*412dd5c5SVarun Wadekar * 18*412dd5c5SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*412dd5c5SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*412dd5c5SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*412dd5c5SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*412dd5c5SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*412dd5c5SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*412dd5c5SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*412dd5c5SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*412dd5c5SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*412dd5c5SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*412dd5c5SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*412dd5c5SVarun Wadekar */ 30*412dd5c5SVarun Wadekar 31*412dd5c5SVarun Wadekar #ifndef __MEMCTRLV2_H__ 32*412dd5c5SVarun Wadekar #define __MEMCTRLV2_H__ 33*412dd5c5SVarun Wadekar 34*412dd5c5SVarun Wadekar #include <mmio.h> 35*412dd5c5SVarun Wadekar #include <tegra_def.h> 36*412dd5c5SVarun Wadekar 37*412dd5c5SVarun Wadekar /******************************************************************************* 38*412dd5c5SVarun Wadekar * StreamID to indicate no SMMU translations (requests to be steered on the 39*412dd5c5SVarun Wadekar * SMMU bypass path) 40*412dd5c5SVarun Wadekar ******************************************************************************/ 41*412dd5c5SVarun Wadekar #define MC_STREAM_ID_MAX 0x7F 42*412dd5c5SVarun Wadekar 43*412dd5c5SVarun Wadekar /******************************************************************************* 44*412dd5c5SVarun Wadekar * Stream ID Override Config registers 45*412dd5c5SVarun Wadekar ******************************************************************************/ 46*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0 47*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70 48*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8 49*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0 50*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0 51*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8 52*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 53*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 54*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 55*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 56*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 57*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 58*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 59*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 60*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 61*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 62*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 63*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 64*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 65*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 66*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 67*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 68*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 69*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 70*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 71*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 72*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 73*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 74*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 75*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 76*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 77*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 78*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 79*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 80*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 81*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 82*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 83*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 84*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 85*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 86*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 87*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 88*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 89*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 90*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 91*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 92*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 93*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 94*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 95*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 96*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 97*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 98*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 99*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 100*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 101*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 102*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 103*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 104*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 105*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 106*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 107*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 108*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 109*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 110*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 111*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 112*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 113*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 114*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 115*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 116*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 117*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 118*412dd5c5SVarun Wadekar #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 119*412dd5c5SVarun Wadekar 120*412dd5c5SVarun Wadekar /******************************************************************************* 121*412dd5c5SVarun Wadekar * Stream ID Security Config registers 122*412dd5c5SVarun Wadekar ******************************************************************************/ 123*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_PTCR 0x4 124*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AFIR 0x74 125*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HDAR 0xAC 126*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4 127*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4 128*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SATAR 0xFC 129*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC 130*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C 131*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C 132*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AFIW 0x18C 133*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC 134*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC 135*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPRA 0x224 136*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPWA 0x234 137*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C 138*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254 139*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C 140*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264 141*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C 142*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4 143*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC 144*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4 145*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC 146*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304 147*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C 148*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314 149*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C 150*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324 151*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C 152*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334 153*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C 154*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSRD 0x364 155*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C 156*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VIW 0x394 157*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4 158*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC 159*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APER 0x3D4 160*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEW 0x3DC 161*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4 162*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC 163*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SESRD 0x404 164*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SESWR 0x40C 165*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ETRR 0x424 166*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_ETRW 0x42C 167*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434 168*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C 169*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444 170*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C 171*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AXISR 0x464 172*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AXISW 0x46C 173*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_EQOSR 0x474 174*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C 175*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484 176*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C 177*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494 178*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C 179*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4 180*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC 181*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4 182*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONR 0x4BC 183*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONW 0x4C4 184*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC 185*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4 186*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCER 0x4DC 187*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4 188*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC 189*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4 190*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC 191*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504 192*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C 193*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514 194*412dd5c5SVarun Wadekar #define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C 195*412dd5c5SVarun Wadekar 196*412dd5c5SVarun Wadekar /******************************************************************************* 197*412dd5c5SVarun Wadekar * Memory Controller SMMU Bypass config register 198*412dd5c5SVarun Wadekar ******************************************************************************/ 199*412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG 0x1820 200*412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CTRL_MASK 0x3 201*412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CTRL_SHIFT 0 202*412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 203*412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 204*412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 205*412dd5c5SVarun Wadekar #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 206*412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 207*412dd5c5SVarun Wadekar #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 208*412dd5c5SVarun Wadekar MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 209*412dd5c5SVarun Wadekar 210*412dd5c5SVarun Wadekar /******************************************************************************* 211*412dd5c5SVarun Wadekar * Memory Controller SMMU Global Secure Aux. Configuration Register 212*412dd5c5SVarun Wadekar ******************************************************************************/ 213*412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_SECURE_ACR 0x10 214*412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_SHIFT 16 215*412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_4K (0 << ARM_SMMU_GSR0_PGSIZE_SHIFT) 216*412dd5c5SVarun Wadekar #define ARM_SMMU_GSR0_PGSIZE_64K (1 << ARM_SMMU_GSR0_PGSIZE_SHIFT) 217*412dd5c5SVarun Wadekar 218*412dd5c5SVarun Wadekar /******************************************************************************* 219*412dd5c5SVarun Wadekar * Structure to hold the Stream ID to use to override client inputs 220*412dd5c5SVarun Wadekar ******************************************************************************/ 221*412dd5c5SVarun Wadekar typedef struct mc_streamid_override_cfg { 222*412dd5c5SVarun Wadekar uint32_t offset; 223*412dd5c5SVarun Wadekar uint8_t stream_id; 224*412dd5c5SVarun Wadekar } mc_streamid_override_cfg_t; 225*412dd5c5SVarun Wadekar 226*412dd5c5SVarun Wadekar /******************************************************************************* 227*412dd5c5SVarun Wadekar * Structure to hold the Stream ID Security Configuration settings 228*412dd5c5SVarun Wadekar ******************************************************************************/ 229*412dd5c5SVarun Wadekar typedef struct mc_streamid_security_cfg { 230*412dd5c5SVarun Wadekar char *name; 231*412dd5c5SVarun Wadekar uint32_t offset; 232*412dd5c5SVarun Wadekar int override_enable; 233*412dd5c5SVarun Wadekar int override_client_inputs; 234*412dd5c5SVarun Wadekar int override_client_ns_flag; 235*412dd5c5SVarun Wadekar } mc_streamid_security_cfg_t; 236*412dd5c5SVarun Wadekar 237*412dd5c5SVarun Wadekar #define OVERRIDE_DISABLE 1 238*412dd5c5SVarun Wadekar #define OVERRIDE_ENABLE 0 239*412dd5c5SVarun Wadekar #define CLIENT_FLAG_SECURE 0 240*412dd5c5SVarun Wadekar #define CLIENT_FLAG_NON_SECURE 1 241*412dd5c5SVarun Wadekar #define CLIENT_INPUTS_OVERRIDE 1 242*412dd5c5SVarun Wadekar #define CLIENT_INPUTS_NO_OVERRIDE 0 243*412dd5c5SVarun Wadekar 244*412dd5c5SVarun Wadekar #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 245*412dd5c5SVarun Wadekar { \ 246*412dd5c5SVarun Wadekar .name = # off, \ 247*412dd5c5SVarun Wadekar .offset = MC_STREAMID_SECURITY_CFG_ ## off, \ 248*412dd5c5SVarun Wadekar .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 249*412dd5c5SVarun Wadekar .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 250*412dd5c5SVarun Wadekar .override_enable = OVERRIDE_ ## access \ 251*412dd5c5SVarun Wadekar } 252*412dd5c5SVarun Wadekar 253*412dd5c5SVarun Wadekar /******************************************************************************* 254*412dd5c5SVarun Wadekar * TZDRAM carveout configuration registers 255*412dd5c5SVarun Wadekar ******************************************************************************/ 256*412dd5c5SVarun Wadekar #define MC_SECURITY_CFG0_0 0x70 257*412dd5c5SVarun Wadekar #define MC_SECURITY_CFG1_0 0x74 258*412dd5c5SVarun Wadekar #define MC_SECURITY_CFG3_0 0x9BC 259*412dd5c5SVarun Wadekar 260*412dd5c5SVarun Wadekar /******************************************************************************* 261*412dd5c5SVarun Wadekar * Video Memory carveout configuration registers 262*412dd5c5SVarun Wadekar ******************************************************************************/ 263*412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_HI 0x978 264*412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_BASE_LO 0x648 265*412dd5c5SVarun Wadekar #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 266*412dd5c5SVarun Wadekar 267*412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_read_32(uint32_t off) 268*412dd5c5SVarun Wadekar { 269*412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 270*412dd5c5SVarun Wadekar } 271*412dd5c5SVarun Wadekar 272*412dd5c5SVarun Wadekar static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 273*412dd5c5SVarun Wadekar { 274*412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 275*412dd5c5SVarun Wadekar } 276*412dd5c5SVarun Wadekar 277*412dd5c5SVarun Wadekar static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 278*412dd5c5SVarun Wadekar { 279*412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 280*412dd5c5SVarun Wadekar } 281*412dd5c5SVarun Wadekar 282*412dd5c5SVarun Wadekar static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 283*412dd5c5SVarun Wadekar { 284*412dd5c5SVarun Wadekar mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 285*412dd5c5SVarun Wadekar } 286*412dd5c5SVarun Wadekar 287*412dd5c5SVarun Wadekar static inline uint32_t tegra_smmu_read_32(uint32_t off) 288*412dd5c5SVarun Wadekar { 289*412dd5c5SVarun Wadekar return mmio_read_32(TEGRA_SMMU_BASE + off); 290*412dd5c5SVarun Wadekar } 291*412dd5c5SVarun Wadekar 292*412dd5c5SVarun Wadekar static inline void tegra_smmu_write_32(uint32_t off, uint32_t val) 293*412dd5c5SVarun Wadekar { 294*412dd5c5SVarun Wadekar mmio_write_32(TEGRA_SMMU_BASE + off, val); 295*412dd5c5SVarun Wadekar } 296*412dd5c5SVarun Wadekar 297*412dd5c5SVarun Wadekar #endif /* __MEMCTRLV2_H__ */ 298