Merge changes from topic "tegra-downstream-03192020" into integration

* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support

Merge changes from topic "tegra-downstream-03192020" into integration

* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support new TLK SMCs for RPMB service
Tegra210: trigger CPU0 hotplug power on using FC
Tegra: memctrl: cleanup streamid override registers
Tegra: memctrl_v2: remove support to secure TZSRAM
Tegra: include platform headers from individual makefiles
Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
Tegra194: SiP function ID to read SMMU_PER registers
Tegra: memctrl: map video memory as uncached
Tegra: remove support for USE_COHERENT_MEM
Tegra: remove circular dependency with common_def.h
Tegra: include missing stdbool.h
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

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Tegra: include missing stdbool.h

This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.

Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wad

Tegra: include missing stdbool.h

This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.

Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19

Tf2.0 tegra downstream rebase 1.25.19

Tegra: support for System Suspend using sc7entry-fw binary

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no long

Tegra: support for System Suspend using sc7entry-fw binary

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock()

Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate
* tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate
* tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU?

Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the fl

Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.

This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.

Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #925 from dp-arm/dp/spdx

Use SPDX license identifiers

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Merge branch 'integration' into tf_issue_461

Merge pull request #899 from vwadekar/tegra186-platform-support-v6

Tegra186 platform support v6

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MI

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.

Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #452 from vwadekar/tegra-new-platform-apis-v2

Tegra new platform apis v2

Tegra: flowctrl: rename tegra_fc_cpu_idle() to tegra_fc_cpu_powerdn()

This patch renames the tegra_fc_cpu_idle() function to a more appropriate
tegra_fc_cpu_powerdn() to better reflect its usage.

S

Tegra: flowctrl: rename tegra_fc_cpu_idle() to tegra_fc_cpu_powerdn()

This patch renames the tegra_fc_cpu_idle() function to a more appropriate
tegra_fc_cpu_powerdn() to better reflect its usage.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #308 from vwadekar/tegra-soc-support-v4

Tegra soc support v4

Support for NVIDIA's Tegra T210 SoCs

T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given

Support for NVIDIA's Tegra T210 SoCs

T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.

This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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