108438e24SVarun Wadekar /* 250e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 708438e24SVarun Wadekar #ifndef __FLOWCTRL_H__ 808438e24SVarun Wadekar #define __FLOWCTRL_H__ 908438e24SVarun Wadekar 1008438e24SVarun Wadekar #include <mmio.h> 1108438e24SVarun Wadekar #include <tegra_def.h> 1208438e24SVarun Wadekar 1350e91633SAnthony Zhou #define FLOWCTRL_HALT_CPU0_EVENTS 0x0U 1450e91633SAnthony Zhou #define FLOWCTRL_WAITEVENT (2U << 29) 1550e91633SAnthony Zhou #define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29) 1650e91633SAnthony Zhou #define FLOWCTRL_JTAG_RESUME (1U << 28) 1750e91633SAnthony Zhou #define FLOWCTRL_HALT_SCLK (1U << 27) 1850e91633SAnthony Zhou #define FLOWCTRL_HALT_LIC_IRQ (1U << 11) 1950e91633SAnthony Zhou #define FLOWCTRL_HALT_LIC_FIQ (1U << 10) 2050e91633SAnthony Zhou #define FLOWCTRL_HALT_GIC_IRQ (1U << 9) 2150e91633SAnthony Zhou #define FLOWCTRL_HALT_GIC_FIQ (1U << 8) 2250e91633SAnthony Zhou #define FLOWCTRL_HALT_BPMP_EVENTS 0x4U 2350e91633SAnthony Zhou #define FLOWCTRL_CPU0_CSR 0x8U 2450e91633SAnthony Zhou #define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16) 2550e91633SAnthony Zhou #define FLOWCTRL_CSR_INTR_FLAG (1U << 15) 2650e91633SAnthony Zhou #define FLOWCTRL_CSR_EVENT_FLAG (1U << 14) 2750e91633SAnthony Zhou #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3) 2850e91633SAnthony Zhou #define FLOWCTRL_CSR_ENABLE (1U << 0) 2950e91633SAnthony Zhou #define FLOWCTRL_HALT_CPU1_EVENTS 0x14U 3050e91633SAnthony Zhou #define FLOWCTRL_CPU1_CSR 0x18U 3150e91633SAnthony Zhou #define FLOWCTRL_CC4_CORE0_CTRL 0x6cU 3250e91633SAnthony Zhou #define FLOWCTRL_WAIT_WFI_BITMAP 0x100U 3350e91633SAnthony Zhou #define FLOWCTRL_L2_FLUSH_CONTROL 0x94U 3450e91633SAnthony Zhou #define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U 3550e91633SAnthony Zhou #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2) 3608438e24SVarun Wadekar 3750e91633SAnthony Zhou #define FLOWCTRL_ENABLE_EXT 12U 3850e91633SAnthony Zhou #define FLOWCTRL_ENABLE_EXT_MASK 3U 3950e91633SAnthony Zhou #define FLOWCTRL_PG_CPU_NONCPU 0x1U 4050e91633SAnthony Zhou #define FLOWCTRL_TURNOFF_CPURAIL 0x2U 4108438e24SVarun Wadekar 4208438e24SVarun Wadekar static inline uint32_t tegra_fc_read_32(uint32_t off) 4308438e24SVarun Wadekar { 4408438e24SVarun Wadekar return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); 4508438e24SVarun Wadekar } 4608438e24SVarun Wadekar 4708438e24SVarun Wadekar static inline void tegra_fc_write_32(uint32_t off, uint32_t val) 4808438e24SVarun Wadekar { 4908438e24SVarun Wadekar mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); 5008438e24SVarun Wadekar } 5108438e24SVarun Wadekar 5208438e24SVarun Wadekar void tegra_fc_cluster_idle(uint32_t midr); 53864ab0fdSVarun Wadekar void tegra_fc_cpu_powerdn(uint32_t mpidr); 5408438e24SVarun Wadekar void tegra_fc_cluster_powerdn(uint32_t midr); 5508438e24SVarun Wadekar void tegra_fc_soc_powerdn(uint32_t midr); 5608438e24SVarun Wadekar void tegra_fc_cpu_on(int cpu); 5708438e24SVarun Wadekar void tegra_fc_cpu_off(int cpu); 5808438e24SVarun Wadekar void tegra_fc_lock_active_cluster(void); 5908438e24SVarun Wadekar void tegra_fc_reset_bpmp(void); 6008438e24SVarun Wadekar 6108438e24SVarun Wadekar #endif /* __FLOWCTRL_H__ */ 62