108438e24SVarun Wadekar /* 2*50e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar #ifndef __FLOWCTRL_H__ 3208438e24SVarun Wadekar #define __FLOWCTRL_H__ 3308438e24SVarun Wadekar 3408438e24SVarun Wadekar #include <mmio.h> 3508438e24SVarun Wadekar #include <tegra_def.h> 3608438e24SVarun Wadekar 37*50e91633SAnthony Zhou #define FLOWCTRL_HALT_CPU0_EVENTS 0x0U 38*50e91633SAnthony Zhou #define FLOWCTRL_WAITEVENT (2U << 29) 39*50e91633SAnthony Zhou #define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29) 40*50e91633SAnthony Zhou #define FLOWCTRL_JTAG_RESUME (1U << 28) 41*50e91633SAnthony Zhou #define FLOWCTRL_HALT_SCLK (1U << 27) 42*50e91633SAnthony Zhou #define FLOWCTRL_HALT_LIC_IRQ (1U << 11) 43*50e91633SAnthony Zhou #define FLOWCTRL_HALT_LIC_FIQ (1U << 10) 44*50e91633SAnthony Zhou #define FLOWCTRL_HALT_GIC_IRQ (1U << 9) 45*50e91633SAnthony Zhou #define FLOWCTRL_HALT_GIC_FIQ (1U << 8) 46*50e91633SAnthony Zhou #define FLOWCTRL_HALT_BPMP_EVENTS 0x4U 47*50e91633SAnthony Zhou #define FLOWCTRL_CPU0_CSR 0x8U 48*50e91633SAnthony Zhou #define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16) 49*50e91633SAnthony Zhou #define FLOWCTRL_CSR_INTR_FLAG (1U << 15) 50*50e91633SAnthony Zhou #define FLOWCTRL_CSR_EVENT_FLAG (1U << 14) 51*50e91633SAnthony Zhou #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3) 52*50e91633SAnthony Zhou #define FLOWCTRL_CSR_ENABLE (1U << 0) 53*50e91633SAnthony Zhou #define FLOWCTRL_HALT_CPU1_EVENTS 0x14U 54*50e91633SAnthony Zhou #define FLOWCTRL_CPU1_CSR 0x18U 55*50e91633SAnthony Zhou #define FLOWCTRL_CC4_CORE0_CTRL 0x6cU 56*50e91633SAnthony Zhou #define FLOWCTRL_WAIT_WFI_BITMAP 0x100U 57*50e91633SAnthony Zhou #define FLOWCTRL_L2_FLUSH_CONTROL 0x94U 58*50e91633SAnthony Zhou #define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U 59*50e91633SAnthony Zhou #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2) 6008438e24SVarun Wadekar 61*50e91633SAnthony Zhou #define FLOWCTRL_ENABLE_EXT 12U 62*50e91633SAnthony Zhou #define FLOWCTRL_ENABLE_EXT_MASK 3U 63*50e91633SAnthony Zhou #define FLOWCTRL_PG_CPU_NONCPU 0x1U 64*50e91633SAnthony Zhou #define FLOWCTRL_TURNOFF_CPURAIL 0x2U 6508438e24SVarun Wadekar 6608438e24SVarun Wadekar static inline uint32_t tegra_fc_read_32(uint32_t off) 6708438e24SVarun Wadekar { 6808438e24SVarun Wadekar return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); 6908438e24SVarun Wadekar } 7008438e24SVarun Wadekar 7108438e24SVarun Wadekar static inline void tegra_fc_write_32(uint32_t off, uint32_t val) 7208438e24SVarun Wadekar { 7308438e24SVarun Wadekar mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); 7408438e24SVarun Wadekar } 7508438e24SVarun Wadekar 7608438e24SVarun Wadekar void tegra_fc_cluster_idle(uint32_t midr); 77864ab0fdSVarun Wadekar void tegra_fc_cpu_powerdn(uint32_t mpidr); 7808438e24SVarun Wadekar void tegra_fc_cluster_powerdn(uint32_t midr); 7908438e24SVarun Wadekar void tegra_fc_soc_powerdn(uint32_t midr); 8008438e24SVarun Wadekar void tegra_fc_cpu_on(int cpu); 8108438e24SVarun Wadekar void tegra_fc_cpu_off(int cpu); 8208438e24SVarun Wadekar void tegra_fc_lock_active_cluster(void); 8308438e24SVarun Wadekar void tegra_fc_reset_bpmp(void); 8408438e24SVarun Wadekar 8508438e24SVarun Wadekar #endif /* __FLOWCTRL_H__ */ 86