1*08438e24SVarun Wadekar /* 2*08438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*08438e24SVarun Wadekar * 4*08438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*08438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*08438e24SVarun Wadekar * 7*08438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*08438e24SVarun Wadekar * list of conditions and the following disclaimer. 9*08438e24SVarun Wadekar * 10*08438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*08438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*08438e24SVarun Wadekar * and/or other materials provided with the distribution. 13*08438e24SVarun Wadekar * 14*08438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*08438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 16*08438e24SVarun Wadekar * prior written permission. 17*08438e24SVarun Wadekar * 18*08438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*08438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*08438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*08438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*08438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*08438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*08438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*08438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*08438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*08438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*08438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*08438e24SVarun Wadekar */ 30*08438e24SVarun Wadekar 31*08438e24SVarun Wadekar #ifndef __FLOWCTRL_H__ 32*08438e24SVarun Wadekar #define __FLOWCTRL_H__ 33*08438e24SVarun Wadekar 34*08438e24SVarun Wadekar #include <mmio.h> 35*08438e24SVarun Wadekar #include <tegra_def.h> 36*08438e24SVarun Wadekar 37*08438e24SVarun Wadekar #define FLOWCTRL_HALT_CPU0_EVENTS 0x0 38*08438e24SVarun Wadekar #define FLOWCTRL_WAITEVENT (2 << 29) 39*08438e24SVarun Wadekar #define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29) 40*08438e24SVarun Wadekar #define FLOWCTRL_JTAG_RESUME (1 << 28) 41*08438e24SVarun Wadekar #define FLOWCTRL_HALT_SCLK (1 << 27) 42*08438e24SVarun Wadekar #define FLOWCTRL_HALT_LIC_IRQ (1 << 11) 43*08438e24SVarun Wadekar #define FLOWCTRL_HALT_LIC_FIQ (1 << 10) 44*08438e24SVarun Wadekar #define FLOWCTRL_HALT_GIC_IRQ (1 << 9) 45*08438e24SVarun Wadekar #define FLOWCTRL_HALT_GIC_FIQ (1 << 8) 46*08438e24SVarun Wadekar #define FLOWCTRL_HALT_BPMP_EVENTS 0x4 47*08438e24SVarun Wadekar #define FLOWCTRL_CPU0_CSR 0x8 48*08438e24SVarun Wadekar #define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16) 49*08438e24SVarun Wadekar #define FLOWCTRL_CSR_INTR_FLAG (1 << 15) 50*08438e24SVarun Wadekar #define FLOWCTRL_CSR_EVENT_FLAG (1 << 14) 51*08438e24SVarun Wadekar #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3) 52*08438e24SVarun Wadekar #define FLOWCTRL_CSR_ENABLE (1 << 0) 53*08438e24SVarun Wadekar #define FLOWCTRL_HALT_CPU1_EVENTS 0x14 54*08438e24SVarun Wadekar #define FLOWCTRL_CPU1_CSR 0x18 55*08438e24SVarun Wadekar #define FLOWCTRL_CC4_CORE0_CTRL 0x6c 56*08438e24SVarun Wadekar #define FLOWCTRL_WAIT_WFI_BITMAP 0x100 57*08438e24SVarun Wadekar #define FLOWCTRL_L2_FLUSH_CONTROL 0x94 58*08438e24SVarun Wadekar #define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98 59*08438e24SVarun Wadekar #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2) 60*08438e24SVarun Wadekar 61*08438e24SVarun Wadekar #define FLOWCTRL_ENABLE_EXT 12 62*08438e24SVarun Wadekar #define FLOWCTRL_ENABLE_EXT_MASK 3 63*08438e24SVarun Wadekar #define FLOWCTRL_PG_CPU_NONCPU 0x1 64*08438e24SVarun Wadekar #define FLOWCTRL_TURNOFF_CPURAIL 0x2 65*08438e24SVarun Wadekar 66*08438e24SVarun Wadekar static inline uint32_t tegra_fc_read_32(uint32_t off) 67*08438e24SVarun Wadekar { 68*08438e24SVarun Wadekar return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); 69*08438e24SVarun Wadekar } 70*08438e24SVarun Wadekar 71*08438e24SVarun Wadekar static inline void tegra_fc_write_32(uint32_t off, uint32_t val) 72*08438e24SVarun Wadekar { 73*08438e24SVarun Wadekar mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); 74*08438e24SVarun Wadekar } 75*08438e24SVarun Wadekar 76*08438e24SVarun Wadekar void tegra_fc_cpu_idle(uint32_t mpidr); 77*08438e24SVarun Wadekar void tegra_fc_cluster_idle(uint32_t midr); 78*08438e24SVarun Wadekar void tegra_fc_cluster_powerdn(uint32_t midr); 79*08438e24SVarun Wadekar void tegra_fc_soc_powerdn(uint32_t midr); 80*08438e24SVarun Wadekar void tegra_fc_cpu_on(int cpu); 81*08438e24SVarun Wadekar void tegra_fc_cpu_off(int cpu); 82*08438e24SVarun Wadekar void tegra_fc_lock_active_cluster(void); 83*08438e24SVarun Wadekar void tegra_fc_reset_bpmp(void); 84*08438e24SVarun Wadekar 85*08438e24SVarun Wadekar #endif /* __FLOWCTRL_H__ */ 86