1 /* 2 * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <arch_def.h> 14 15 #define PLAT_PRIMARY_CPU (0x0) 16 17 #define MT_GIC_BASE (0x0C400000) 18 #define MCUCFG_BASE (0x0C000000) 19 #define MCUCFG_REG_SIZE (0x50000) 20 #define IO_PHYS (0x10000000) 21 22 /* Aggregate of all devices for MMU mapping */ 23 #define MTK_DEV_RNG1_BASE (IO_PHYS) 24 #define MTK_DEV_RNG1_SIZE (0x10000000) 25 26 #define TOPCKGEN_BASE (IO_PHYS) 27 28 /******************************************************************************* 29 * AUDIO related constants 30 ******************************************************************************/ 31 #define AUDIO_BASE (IO_PHYS + 0x0a110000) 32 33 /******************************************************************************* 34 * APUSYS related constants 35 ******************************************************************************/ 36 #define APUSYS_BASE (IO_PHYS + 0x09000000) 37 #define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000) 38 #define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000) 39 #define APU_CMU_TOP (IO_PHYS + 0x09067000) 40 #define APUSYS_CE_BASE (IO_PHYS + 0x090B0000) 41 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000) 42 #define APU_AO_CTRL (IO_PHYS + 0x090F2000) 43 #define APU_SEC_CON (IO_PHYS + 0x090F5000) 44 #define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000) 45 46 #define APU_MBOX0 (0x4C200000) 47 48 #define APU_MBOX0_SZ (0x100000) 49 #define APU_INFRA_BASE (0x1002C000) 50 #define APU_INFRA_SZ (0x1000) 51 52 /******************************************************************************* 53 * SPM related constants 54 ******************************************************************************/ 55 #define SPM_BASE (IO_PHYS + 0x0C004000) 56 57 /******************************************************************************* 58 * GPIO related constants 59 ******************************************************************************/ 60 #define GPIO_BASE (IO_PHYS + 0x0002D000) 61 #define RGU_BASE (IO_PHYS + 0x0C00B000) 62 #define DRM_BASE (IO_PHYS + 0x0000D000) 63 #define IOCFG_RT_BASE (IO_PHYS + 0x02000000) 64 #define IOCFG_RM1_BASE (IO_PHYS + 0x02020000) 65 #define IOCFG_RM2_BASE (IO_PHYS + 0x02040000) 66 #define IOCFG_RB_BASE (IO_PHYS + 0x02060000) 67 #define IOCFG_BM1_BASE (IO_PHYS + 0x02820000) 68 #define IOCFG_BM2_BASE (IO_PHYS + 0x02840000) 69 #define IOCFG_BM3_BASE (IO_PHYS + 0x02860000) 70 #define IOCFG_LT_BASE (IO_PHYS + 0x03000000) 71 #define IOCFG_LM1_BASE (IO_PHYS + 0x03020000) 72 #define IOCFG_LM2_BASE (IO_PHYS + 0x03040000) 73 #define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000) 74 #define IOCFG_LB2_BASE (IO_PHYS + 0x03110000) 75 #define IOCFG_TM1_BASE (IO_PHYS + 0x03800000) 76 #define IOCFG_TM2_BASE (IO_PHYS + 0x03820000) 77 #define IOCFG_TM3_BASE (IO_PHYS + 0x03860000) 78 79 /******************************************************************************* 80 * UART related constants 81 ******************************************************************************/ 82 #define UART0_BASE (IO_PHYS + 0x06000000) 83 #define UART_BAUDRATE (115200) 84 85 /******************************************************************************* 86 * Infra IOMMU related constants 87 ******************************************************************************/ 88 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 89 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 90 #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 91 #define PERICFG_AO_REG_SIZE (0x1000) 92 93 /******************************************************************************* 94 * GIC-600 & interrupt handling related constants 95 ******************************************************************************/ 96 /* Base MTK_platform compatible GIC memory map */ 97 #define BASE_GICD_BASE (MT_GIC_BASE) 98 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 99 #define MTK_GIC_REG_SIZE 0x400000 100 101 /******************************************************************************* 102 * MM IOMMU & SMI related constants 103 ******************************************************************************/ 104 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 105 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 106 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 107 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 108 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 109 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 110 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 111 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 112 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 113 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 114 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 115 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 116 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 117 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 118 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 119 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 120 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 121 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 122 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 123 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 124 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 125 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 126 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 127 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 128 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 129 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 130 #define SMI_LARB_REG_RNG_SIZE (0x1000) 131 132 /******************************************************************************* 133 * APMIXEDSYS related constants 134 ******************************************************************************/ 135 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 136 137 /******************************************************************************* 138 * VPPSYS related constants 139 ******************************************************************************/ 140 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 141 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 142 143 /******************************************************************************* 144 * VDOSYS related constants 145 ******************************************************************************/ 146 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 147 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 148 149 /******************************************************************************* 150 * DP related constants 151 ******************************************************************************/ 152 #define EDP_SEC_BASE (IO_PHYS + 0x2EC50000) 153 #define DP_SEC_BASE (IO_PHYS + 0x2EC10000) 154 #define EDP_SEC_SIZE (0x1000) 155 #define DP_SEC_SIZE (0x1000) 156 157 /******************************************************************************* 158 * EMI MPU related constants 159 *******************************************************************************/ 160 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 161 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 162 163 /******************************************************************************* 164 * System counter frequency related constants 165 ******************************************************************************/ 166 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 167 #define SYS_COUNTER_FREQ_IN_MHZ (13) 168 169 /******************************************************************************* 170 * Generic platform constants 171 ******************************************************************************/ 172 #define PLATFORM_STACK_SIZE (0x800) 173 #define SOC_CHIP_ID U(0x8196) 174 175 /******************************************************************************* 176 * Platform memory map related constants 177 ******************************************************************************/ 178 #define TZRAM_BASE (0x94600000) 179 #define TZRAM_SIZE (0x00200000) 180 181 /******************************************************************************* 182 * BL31 specific defines. 183 ******************************************************************************/ 184 /* 185 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 186 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 187 * little space for growth. 188 */ 189 #define BL31_BASE (TZRAM_BASE + 0x1000) 190 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 191 192 /******************************************************************************* 193 * Platform specific page table and MMU setup constants 194 ******************************************************************************/ 195 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 196 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 197 #define MAX_XLAT_TABLES (128) 198 #define MAX_MMAP_REGIONS (512) 199 200 /******************************************************************************* 201 * CPU PM definitions 202 *******************************************************************************/ 203 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 204 #define PLAT_CPU_PM_ILDO_ID (6) 205 #define CPU_IDLE_SRAM_BASE (0x11B000) 206 #define CPU_IDLE_SRAM_SIZE (0x1000) 207 208 /******************************************************************************* 209 * SYSTIMER related definitions 210 ******************************************************************************/ 211 #define SYSTIMER_BASE (0x1C400000) 212 213 #endif /* PLATFORM_DEF_H */ 214