1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <arch_def.h> 14 15 #define PLAT_PRIMARY_CPU (0x0) 16 17 #define MT_GIC_BASE (0x0C400000) 18 #define MCUCFG_BASE (0x0C000000) 19 #define MCUCFG_REG_SIZE (0x50000) 20 #define IO_PHYS (0x10000000) 21 22 #define MT_UTILITYBUS_BASE (0x0C800000) 23 #define MT_UTILITYBUS_SIZE (0x800000) 24 25 /* Aggregate of all devices for MMU mapping */ 26 #define MTK_DEV_RNG1_BASE (IO_PHYS) 27 #define MTK_DEV_RNG1_SIZE (0x10000000) 28 29 #define TOPCKGEN_BASE (IO_PHYS) 30 31 /******************************************************************************* 32 * AUDIO related constants 33 ******************************************************************************/ 34 #define AUDIO_BASE (IO_PHYS + 0x0a110000) 35 36 /******************************************************************************* 37 * APUSYS related constants 38 ******************************************************************************/ 39 #define APUSYS_BASE (IO_PHYS + 0x09000000) 40 #define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000) 41 #define APU_MD32_WDT (IO_PHYS + 0x09002000) 42 #define APU_LOGTOP (IO_PHYS + 0x09024000) 43 #define APUSYS_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09030000) 44 #define APU_REVISER (IO_PHYS + 0x0903C000) 45 #define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000) 46 #define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000) 47 #define APU_CMU_TOP (IO_PHYS + 0x09067000) 48 #define APUSYS_CE_BASE (IO_PHYS + 0x090B0000) 49 #define APU_ARE_REG_BASE (IO_PHYS + 0x090B0000) 50 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000) 51 #define APU_AO_CTRL (IO_PHYS + 0x090F2000) 52 #define APU_SEC_CON (IO_PHYS + 0x090F5000) 53 #define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000) 54 55 #define APU_MBOX0 (0x4C200000) 56 #define APU_MD32_TCM (0x4D000000) 57 58 #define APU_MD32_TCM_SZ (0x50000) 59 #define APU_MBOX0_SZ (0x100000) 60 #define APU_INFRA_BASE (0x1002C000) 61 #define APU_INFRA_SZ (0x1000) 62 63 #define APU_RESERVE_MEMORY (0x95000000) 64 #define APU_SEC_INFO_OFFSET (0x100000) 65 #define APU_RESERVE_SIZE (0x1400000) 66 #define APUSYS_CE_MEM_BASE (0x190A4400) 67 #define APUSYS_CE_MEM_SIZE (0x3000) 68 #define APUSYS_ACE_HW_CONFG_BASE (0x190A0050) 69 #define APUSYS_ACE_HW_CONFG_SIZE (0x20) 70 71 /******************************************************************************* 72 * SPM related constants 73 ******************************************************************************/ 74 #define SPM_BASE (IO_PHYS + 0x0C004000) 75 #define SPM_REG_SIZE (0x1000) 76 #define SPM_SRAM_BASE (IO_PHYS + 0x0C00C000) 77 #define SPM_SRAM_REG_SIZE (0x1000) 78 #define SPM_PBUS_BASE (IO_PHYS + 0x0C00D000) 79 #define SPM_PBUS_REG_SIZE (0x1000) 80 81 #ifdef SPM_BASE 82 #define SPM_EXT_INT_WAKEUP_REQ (SPM_BASE + 0x210) 83 #define SPM_EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x214) 84 #define SPM_EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x218) 85 #define SPM_CPU_BUCK_ISO_CON (SPM_BASE + 0xEF8) 86 #define SPM_CPU_BUCK_ISO_DEFAUT (0x0) 87 #define SPM_AUDIO_PWR_CON (SPM_BASE + 0xE4C) 88 #endif 89 90 /******************************************************************************* 91 * GPIO related constants 92 ******************************************************************************/ 93 #define GPIO_BASE (IO_PHYS + 0x0002D000) 94 #define RGU_BASE (IO_PHYS + 0x0C010000) 95 #define DRM_BASE (IO_PHYS + 0x0000D000) 96 #define IOCFG_RT_BASE (IO_PHYS + 0x02000000) 97 #define IOCFG_RM1_BASE (IO_PHYS + 0x02020000) 98 #define IOCFG_RM2_BASE (IO_PHYS + 0x02040000) 99 #define IOCFG_RB_BASE (IO_PHYS + 0x02060000) 100 #define IOCFG_BM1_BASE (IO_PHYS + 0x02820000) 101 #define IOCFG_BM2_BASE (IO_PHYS + 0x02840000) 102 #define IOCFG_BM3_BASE (IO_PHYS + 0x02860000) 103 #define IOCFG_LT_BASE (IO_PHYS + 0x03000000) 104 #define IOCFG_LM1_BASE (IO_PHYS + 0x03020000) 105 #define IOCFG_LM2_BASE (IO_PHYS + 0x03040000) 106 #define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000) 107 #define IOCFG_LB2_BASE (IO_PHYS + 0x03110000) 108 #define IOCFG_TM1_BASE (IO_PHYS + 0x03800000) 109 #define IOCFG_TM2_BASE (IO_PHYS + 0x03820000) 110 #define IOCFG_TM3_BASE (IO_PHYS + 0x03860000) 111 112 /******************************************************************************* 113 * UART related constants 114 ******************************************************************************/ 115 #define UART0_BASE (IO_PHYS + 0x06000000) 116 #define UART_BAUDRATE (115200) 117 118 /******************************************************************************* 119 * PMIF address 120 ******************************************************************************/ 121 #define PMIF_SPMI_M_BASE (IO_PHYS + 0x0C01A000) 122 #define PMIF_SPMI_P_BASE (IO_PHYS + 0x0C018000) 123 #define PMIF_SPMI_SIZE 0x1000 124 125 /******************************************************************************* 126 * SPMI address 127 ******************************************************************************/ 128 #define SPMI_MST_M_BASE (IO_PHYS + 0x0C01C000) 129 #define SPMI_MST_P_BASE (IO_PHYS + 0x0C01C800) 130 #define SPMI_MST_SIZE 0x1000 131 132 /******************************************************************************* 133 * Infra IOMMU related constants 134 ******************************************************************************/ 135 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 136 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 137 #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 138 #define PERICFG_AO_REG_SIZE (0x1000) 139 140 /******************************************************************************* 141 * GIC-600 & interrupt handling related constants 142 ******************************************************************************/ 143 /* Base MTK_platform compatible GIC memory map */ 144 #define BASE_GICD_BASE (MT_GIC_BASE) 145 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 146 #define MTK_GIC_REG_SIZE 0x400000 147 #define SGI_MASK 0xffff 148 #define DEV_IRQ_ID 982 149 150 #define PLATFORM_G1S_PROPS(grp) \ 151 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 152 GIC_INTR_CFG_LEVEL) 153 154 /******************************************************************************* 155 * CIRQ related constants 156 ******************************************************************************/ 157 #define SYS_CIRQ_BASE (IO_PHYS + 0x1CB000) 158 #define MD_WDT_IRQ_BIT_ID (397) 159 #define CIRQ_REG_NUM (26) 160 #define CIRQ_SPI_START (128) 161 #define CIRQ_IRQ_NUM (831) 162 163 /******************************************************************************* 164 * MM IOMMU & SMI related constants 165 ******************************************************************************/ 166 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 167 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 168 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 169 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 170 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 171 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 172 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 173 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 174 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 175 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 176 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 177 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 178 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 179 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 180 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 181 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 182 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 183 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 184 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 185 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 186 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 187 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 188 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 189 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 190 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 191 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 192 #define SMI_LARB_REG_RNG_SIZE (0x1000) 193 194 /******************************************************************************* 195 * APMIXEDSYS related constants 196 ******************************************************************************/ 197 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 198 199 /******************************************************************************* 200 * VPPSYS related constants 201 ******************************************************************************/ 202 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 203 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 204 205 /******************************************************************************* 206 * VDOSYS related constants 207 ******************************************************************************/ 208 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 209 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 210 211 /******************************************************************************* 212 * DP related constants 213 ******************************************************************************/ 214 #define EDP_SEC_BASE (IO_PHYS + 0x2EC54000) 215 #define DP_SEC_BASE (IO_PHYS + 0x2EC14000) 216 #define EDP_SEC_SIZE (0x1000) 217 #define DP_SEC_SIZE (0x1000) 218 219 /******************************************************************************* 220 * EMI MPU related constants 221 *******************************************************************************/ 222 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 223 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 224 #define EMI_SLB_BASE (IO_PHYS + 0x0042e000) 225 #define SUB_EMI_SLB_BASE (IO_PHYS + 0x0052e000) 226 #define CHN0_EMI_APB_BASE (IO_PHYS + 0x00201000) 227 #define CHN1_EMI_APB_BASE (IO_PHYS + 0x00205000) 228 #define CHN2_EMI_APB_BASE (IO_PHYS + 0x00209000) 229 #define CHN3_EMI_APB_BASE (IO_PHYS + 0x0020D000) 230 #define EMI_APB_BASE (IO_PHYS + 0x00429000) 231 #define INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00425000) 232 #define NEMI_SMPU_BASE (IO_PHYS + 0x0042f000) 233 #define SEMI_SMPU_BASE (IO_PHYS + 0x0052f000) 234 #define SUB_EMI_APB_BASE (IO_PHYS + 0x00529000) 235 #define SUB_INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00525000) 236 #define SUB_INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00504000) 237 #define EMI_MPU_ALIGN_BITS 12 238 239 /******************************************************************************* 240 * System counter frequency related constants 241 ******************************************************************************/ 242 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 243 #define SYS_COUNTER_FREQ_IN_MHZ (13) 244 245 /******************************************************************************* 246 * Generic platform constants 247 ******************************************************************************/ 248 #define PLATFORM_STACK_SIZE (0x800) 249 #define SOC_CHIP_ID U(0x8196) 250 251 /******************************************************************************* 252 * Platform memory map related constants 253 ******************************************************************************/ 254 #define TZRAM_BASE (0x94600000) 255 #define TZRAM_SIZE (0x00200000) 256 257 /******************************************************************************* 258 * BL31 specific defines. 259 ******************************************************************************/ 260 /* 261 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 262 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 263 * little space for growth. 264 */ 265 #define BL31_BASE (TZRAM_BASE + 0x1000) 266 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 267 268 /******************************************************************************* 269 * Platform specific page table and MMU setup constants 270 ******************************************************************************/ 271 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 272 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 273 #define MAX_XLAT_TABLES (128) 274 #define MAX_MMAP_REGIONS (512) 275 276 /******************************************************************************* 277 * CPU_EB TCM handling related constants 278 ******************************************************************************/ 279 #define CPU_EB_TCM_BASE 0x0C2CF000 280 #define CPU_EB_TCM_SIZE 0x1000 281 #define CPU_EB_TCM_CNT_BASE 0x0C2CC000 282 283 /******************************************************************************* 284 * CPU PM definitions 285 ******************************************************************************/ 286 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 287 #define PLAT_CPU_PM_ILDO_ID (6) 288 289 /******************************************************************************* 290 * SYSTIMER related definitions 291 ******************************************************************************/ 292 #define SYSTIMER_BASE (0x1C400000) 293 294 /******************************************************************************* 295 * CKSYS related constants 296 ******************************************************************************/ 297 #define CKSYS_BASE (IO_PHYS) 298 299 /******************************************************************************* 300 * VLP AO related constants 301 ******************************************************************************/ 302 #define VLPCFG_BUS_BASE (IO_PHYS + 0x0C001000) 303 #define VLPCFG_BUS_SIZE (0x1000) 304 #define VLP_AO_DEVAPC_APB_BASE (IO_PHYS + 0x0C550000) 305 #define VLP_AO_DEVAPC_APB_SIZE (0x1000) 306 307 /******************************************************************************* 308 * SCP registers 309 ******************************************************************************/ 310 #define SCP_CLK_CTRL_BASE (IO_PHYS + 0x0CF21000) 311 #define SCP_CLK_CTRL_SIZE (0x1000) 312 313 #define SCP_CFGREG_BASE (IO_PHYS + 0x0CF24000) 314 #define SCP_CFGREG_SIZE (0x1000) 315 316 /******************************************************************************* 317 * VLP CKSYS related constants 318 ******************************************************************************/ 319 #define VLP_CKSYS_BASE (IO_PHYS + 0x0C016000) 320 #define VLP_CKSYS_SIZE 0x1000 321 322 /******************************************************************************* 323 * PERI related constants use PERI secure address to garuantee access 324 ******************************************************************************/ 325 #define PERICFG_AO_SIZE 0x1000 326 #define PERI_CG0_STA (PERICFG_AO_BASE + 0x10) 327 #define PERI_CLK_CON (PERICFG_AO_BASE + 0x20) 328 #define PERI_CG1_CLR (PERICFG_AO_BASE + 0x30) 329 330 /****************************************************************************** 331 * LPM syssram related constants 332 *****************************************************************************/ 333 #define MTK_LPM_SRAM_BASE 0x11B000 334 #define MTK_LPM_SRAM_MAP_SIZE 0x1000 335 336 /******************************************************************************* 337 * SSPM_MBOX_3 related constants 338 ******************************************************************************/ 339 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x0C380000) 340 #define SSPM_MBOX_3_SIZE 0x1000 341 342 /******************************************************************************* 343 * SSPM related constants 344 ******************************************************************************/ 345 #define SSPM_REG_OFFSET (0x40000) 346 #define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET) 347 #define SSPM_CFGREG_SIZE (0x1000) 348 349 /******************************************************************************* 350 * MMinfra related constants 351 ******************************************************************************/ 352 #define MTK_VLP_TRACER_MON_BASE (IO_PHYS + 0x0c000000) 353 #define MTK_VLP_TRACER_MON_REG_SIZE (0x1000) 354 355 #endif /* PLATFORM_DEF_H */ 356