1 /* 2 * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <arch_def.h> 14 15 #define PLAT_PRIMARY_CPU (0x0) 16 17 #define MT_GIC_BASE (0x0C400000) 18 #define MCUCFG_BASE (0x0C000000) 19 #define MCUCFG_REG_SIZE (0x50000) 20 #define IO_PHYS (0x10000000) 21 22 /* Aggregate of all devices for MMU mapping */ 23 #define MTK_DEV_RNG1_BASE (IO_PHYS) 24 #define MTK_DEV_RNG1_SIZE (0x10000000) 25 26 #define TOPCKGEN_BASE (IO_PHYS) 27 28 /******************************************************************************* 29 * AUDIO related constants 30 ******************************************************************************/ 31 #define AUDIO_BASE (IO_PHYS + 0x0a110000) 32 33 /******************************************************************************* 34 * APUSYS related constants 35 ******************************************************************************/ 36 #define APUSYS_BASE (IO_PHYS + 0x09000000) 37 #define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000) 38 #define APU_MD32_WDT (IO_PHYS + 0x09002000) 39 #define APU_LOGTOP (IO_PHYS + 0x09024000) 40 #define APU_REVISER (IO_PHYS + 0x0903C000) 41 #define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000) 42 #define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000) 43 #define APU_CMU_TOP (IO_PHYS + 0x09067000) 44 #define APUSYS_CE_BASE (IO_PHYS + 0x090B0000) 45 #define APU_ARE_REG_BASE (IO_PHYS + 0x090B0000) 46 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000) 47 #define APU_AO_CTRL (IO_PHYS + 0x090F2000) 48 #define APU_SEC_CON (IO_PHYS + 0x090F5000) 49 #define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000) 50 51 #define APU_MBOX0 (0x4C200000) 52 #define APU_MD32_TCM (0x4D000000) 53 54 #define APU_MD32_TCM_SZ (0x50000) 55 #define APU_MBOX0_SZ (0x100000) 56 #define APU_INFRA_BASE (0x1002C000) 57 #define APU_INFRA_SZ (0x1000) 58 59 #define APU_RESERVE_MEMORY (0x95000000) 60 #define APU_SEC_INFO_OFFSET (0x100000) 61 #define APU_RESERVE_SIZE (0x1400000) 62 63 /******************************************************************************* 64 * SPM related constants 65 ******************************************************************************/ 66 #define SPM_BASE (IO_PHYS + 0x0C004000) 67 68 /******************************************************************************* 69 * GPIO related constants 70 ******************************************************************************/ 71 #define GPIO_BASE (IO_PHYS + 0x0002D000) 72 #define RGU_BASE (IO_PHYS + 0x0C00B000) 73 #define DRM_BASE (IO_PHYS + 0x0000D000) 74 #define IOCFG_RT_BASE (IO_PHYS + 0x02000000) 75 #define IOCFG_RM1_BASE (IO_PHYS + 0x02020000) 76 #define IOCFG_RM2_BASE (IO_PHYS + 0x02040000) 77 #define IOCFG_RB_BASE (IO_PHYS + 0x02060000) 78 #define IOCFG_BM1_BASE (IO_PHYS + 0x02820000) 79 #define IOCFG_BM2_BASE (IO_PHYS + 0x02840000) 80 #define IOCFG_BM3_BASE (IO_PHYS + 0x02860000) 81 #define IOCFG_LT_BASE (IO_PHYS + 0x03000000) 82 #define IOCFG_LM1_BASE (IO_PHYS + 0x03020000) 83 #define IOCFG_LM2_BASE (IO_PHYS + 0x03040000) 84 #define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000) 85 #define IOCFG_LB2_BASE (IO_PHYS + 0x03110000) 86 #define IOCFG_TM1_BASE (IO_PHYS + 0x03800000) 87 #define IOCFG_TM2_BASE (IO_PHYS + 0x03820000) 88 #define IOCFG_TM3_BASE (IO_PHYS + 0x03860000) 89 90 /******************************************************************************* 91 * UART related constants 92 ******************************************************************************/ 93 #define UART0_BASE (IO_PHYS + 0x06000000) 94 #define UART_BAUDRATE (115200) 95 96 /******************************************************************************* 97 * Infra IOMMU related constants 98 ******************************************************************************/ 99 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 100 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 101 #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 102 #define PERICFG_AO_REG_SIZE (0x1000) 103 104 /******************************************************************************* 105 * GIC-600 & interrupt handling related constants 106 ******************************************************************************/ 107 /* Base MTK_platform compatible GIC memory map */ 108 #define BASE_GICD_BASE (MT_GIC_BASE) 109 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 110 #define MTK_GIC_REG_SIZE 0x400000 111 112 /******************************************************************************* 113 * MM IOMMU & SMI related constants 114 ******************************************************************************/ 115 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 116 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 117 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 118 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 119 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 120 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 121 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 122 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 123 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 124 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 125 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 126 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 127 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 128 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 129 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 130 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 131 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 132 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 133 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 134 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 135 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 136 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 137 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 138 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 139 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 140 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 141 #define SMI_LARB_REG_RNG_SIZE (0x1000) 142 143 /******************************************************************************* 144 * APMIXEDSYS related constants 145 ******************************************************************************/ 146 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 147 148 /******************************************************************************* 149 * VPPSYS related constants 150 ******************************************************************************/ 151 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 152 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 153 154 /******************************************************************************* 155 * VDOSYS related constants 156 ******************************************************************************/ 157 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 158 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 159 160 /******************************************************************************* 161 * DP related constants 162 ******************************************************************************/ 163 #define EDP_SEC_BASE (IO_PHYS + 0x2EC50000) 164 #define DP_SEC_BASE (IO_PHYS + 0x2EC10000) 165 #define EDP_SEC_SIZE (0x1000) 166 #define DP_SEC_SIZE (0x1000) 167 168 /******************************************************************************* 169 * EMI MPU related constants 170 *******************************************************************************/ 171 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 172 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 173 174 /******************************************************************************* 175 * System counter frequency related constants 176 ******************************************************************************/ 177 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 178 #define SYS_COUNTER_FREQ_IN_MHZ (13) 179 180 /******************************************************************************* 181 * Generic platform constants 182 ******************************************************************************/ 183 #define PLATFORM_STACK_SIZE (0x800) 184 #define SOC_CHIP_ID U(0x8196) 185 186 /******************************************************************************* 187 * Platform memory map related constants 188 ******************************************************************************/ 189 #define TZRAM_BASE (0x94600000) 190 #define TZRAM_SIZE (0x00200000) 191 192 /******************************************************************************* 193 * BL31 specific defines. 194 ******************************************************************************/ 195 /* 196 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 197 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 198 * little space for growth. 199 */ 200 #define BL31_BASE (TZRAM_BASE + 0x1000) 201 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 202 203 /******************************************************************************* 204 * Platform specific page table and MMU setup constants 205 ******************************************************************************/ 206 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 207 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 208 #define MAX_XLAT_TABLES (128) 209 #define MAX_MMAP_REGIONS (512) 210 211 /******************************************************************************* 212 * CPU PM definitions 213 *******************************************************************************/ 214 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 215 #define PLAT_CPU_PM_ILDO_ID (6) 216 #define CPU_IDLE_SRAM_BASE (0x11B000) 217 #define CPU_IDLE_SRAM_SIZE (0x1000) 218 219 /******************************************************************************* 220 * SYSTIMER related definitions 221 ******************************************************************************/ 222 #define SYSTIMER_BASE (0x1C400000) 223 224 #endif /* PLATFORM_DEF_H */ 225