1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x400000 19 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20 #define MTK_DEV_RNG1_SIZE 0xa110000 21 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22 #define MTK_DEV_RNG2_SIZE 0x600000 23 #define MTK_MCDI_SRAM_BASE 0x11B000 24 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 25 26 #define SPM_BASE (IO_PHYS + 0x00006000) 27 28 /******************************************************************************* 29 * DP/eDP related constants 30 ******************************************************************************/ 31 #define eDP_SEC_BASE (IO_PHYS + 0x0C504000) 32 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 33 #define eDP_SEC_SIZE 0x1000 34 #define DP_SEC_SIZE 0x1000 35 36 /******************************************************************************* 37 * GPIO related constants 38 ******************************************************************************/ 39 #define GPIO_BASE (IO_PHYS + 0x00005000) 40 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 41 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 42 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 43 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 44 #define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000) 45 #define IOCFG_TL_BASE (IO_PHYS + 0x01F40000) 46 47 /******************************************************************************* 48 * UART related constants 49 ******************************************************************************/ 50 #define UART0_BASE (IO_PHYS + 0x01001100) 51 #define UART1_BASE (IO_PHYS + 0x01001200) 52 53 #define UART_BAUDRATE 115200 54 55 /******************************************************************************* 56 * PMIC related constants 57 ******************************************************************************/ 58 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 59 60 /******************************************************************************* 61 * System counter frequency related constants 62 ******************************************************************************/ 63 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 64 #define SYS_COUNTER_FREQ_IN_MHZ 13 65 66 /******************************************************************************* 67 * GIC-600 & interrupt handling related constants 68 ******************************************************************************/ 69 /* Base MTK_platform compatible GIC memory map */ 70 #define BASE_GICD_BASE MT_GIC_BASE 71 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 72 73 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 74 #define CIRQ_REG_NUM 23 75 #define CIRQ_IRQ_NUM 730 76 #define CIRQ_SPI_START 96 77 #define MD_WDT_IRQ_BIT_ID 141 78 /******************************************************************************* 79 * Platform binary types for linking 80 ******************************************************************************/ 81 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 82 #define PLATFORM_LINKER_ARCH aarch64 83 84 /******************************************************************************* 85 * Generic platform constants 86 ******************************************************************************/ 87 #define PLATFORM_STACK_SIZE 0x800 88 89 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 90 91 #define PLAT_MAX_PWR_LVL U(3) 92 #define PLAT_MAX_RET_STATE U(1) 93 #define PLAT_MAX_OFF_STATE U(9) 94 95 #define PLATFORM_SYSTEM_COUNT U(1) 96 #define PLATFORM_MCUSYS_COUNT U(1) 97 #define PLATFORM_CLUSTER_COUNT U(1) 98 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 99 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 100 101 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 102 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 103 104 #define SOC_CHIP_ID U(0x8195) 105 106 /******************************************************************************* 107 * Platform memory map related constants 108 ******************************************************************************/ 109 #define TZRAM_BASE 0x54600000 110 #define TZRAM_SIZE 0x00030000 111 112 /******************************************************************************* 113 * BL31 specific defines. 114 ******************************************************************************/ 115 /* 116 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 117 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 118 * little space for growth. 119 */ 120 #define BL31_BASE (TZRAM_BASE + 0x1000) 121 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 122 123 /******************************************************************************* 124 * Platform specific page table and MMU setup constants 125 ******************************************************************************/ 126 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 127 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 128 #define MAX_XLAT_TABLES 16 129 #define MAX_MMAP_REGIONS 16 130 131 /******************************************************************************* 132 * Declarations and constants to access the mailboxes safely. Each mailbox is 133 * aligned on the biggest cache line size in the platform. This is known only 134 * to the platform as it might have a combination of integrated and external 135 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 136 * line at any cache level. They could belong to different cpus/clusters & 137 * get written while being protected by different locks causing corruption of 138 * a valid mailbox address. 139 ******************************************************************************/ 140 #define CACHE_WRITEBACK_SHIFT 6 141 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 142 #endif /* PLATFORM_DEF_H */ 143