1174a1cfeSYidi Lin /* 2174a1cfeSYidi Lin * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3174a1cfeSYidi Lin * 4174a1cfeSYidi Lin * SPDX-License-Identifier: BSD-3-Clause 5174a1cfeSYidi Lin */ 6174a1cfeSYidi Lin 7174a1cfeSYidi Lin #ifndef PLATFORM_DEF_H 8174a1cfeSYidi Lin #define PLATFORM_DEF_H 9174a1cfeSYidi Lin 10174a1cfeSYidi Lin #define PLAT_PRIMARY_CPU 0x0 11174a1cfeSYidi Lin 12174a1cfeSYidi Lin #define MT_GIC_BASE (0x0C000000) 13174a1cfeSYidi Lin #define MCUCFG_BASE (0x0C530000) 14174a1cfeSYidi Lin #define IO_PHYS (0x10000000) 15174a1cfeSYidi Lin 16174a1cfeSYidi Lin /* Aggregate of all devices for MMU mapping */ 17174a1cfeSYidi Lin #define MTK_DEV_RNG0_BASE IO_PHYS 18174a1cfeSYidi Lin #define MTK_DEV_RNG0_SIZE 0x400000 19174a1cfeSYidi Lin #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20174a1cfeSYidi Lin #define MTK_DEV_RNG1_SIZE 0xa110000 21174a1cfeSYidi Lin #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22174a1cfeSYidi Lin #define MTK_DEV_RNG2_SIZE 0x600000 23174a1cfeSYidi Lin 24174a1cfeSYidi Lin 25174a1cfeSYidi Lin /******************************************************************************* 26174a1cfeSYidi Lin * UART related constants 27174a1cfeSYidi Lin ******************************************************************************/ 28174a1cfeSYidi Lin #define UART0_BASE (IO_PHYS + 0x01001100) 29174a1cfeSYidi Lin #define UART1_BASE (IO_PHYS + 0x01001200) 30174a1cfeSYidi Lin 31174a1cfeSYidi Lin #define UART_BAUDRATE 115200 32174a1cfeSYidi Lin 33174a1cfeSYidi Lin /******************************************************************************* 34174a1cfeSYidi Lin * System counter frequency related constants 35174a1cfeSYidi Lin ******************************************************************************/ 36174a1cfeSYidi Lin #define SYS_COUNTER_FREQ_IN_TICKS 13000000 37174a1cfeSYidi Lin #define SYS_COUNTER_FREQ_IN_MHZ 13 38174a1cfeSYidi Lin 39174a1cfeSYidi Lin /******************************************************************************* 40*c63f1451Schristine.zhu * GIC-600 & interrupt handling related constants 41*c63f1451Schristine.zhu ******************************************************************************/ 42*c63f1451Schristine.zhu /* Base MTK_platform compatible GIC memory map */ 43*c63f1451Schristine.zhu #define BASE_GICD_BASE MT_GIC_BASE 44*c63f1451Schristine.zhu #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 45*c63f1451Schristine.zhu 46*c63f1451Schristine.zhu /******************************************************************************* 47174a1cfeSYidi Lin * Platform binary types for linking 48174a1cfeSYidi Lin ******************************************************************************/ 49174a1cfeSYidi Lin #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 50174a1cfeSYidi Lin #define PLATFORM_LINKER_ARCH aarch64 51174a1cfeSYidi Lin 52174a1cfeSYidi Lin /******************************************************************************* 53174a1cfeSYidi Lin * Generic platform constants 54174a1cfeSYidi Lin ******************************************************************************/ 55174a1cfeSYidi Lin #define PLATFORM_STACK_SIZE 0x800 56174a1cfeSYidi Lin 57174a1cfeSYidi Lin #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 58174a1cfeSYidi Lin 59174a1cfeSYidi Lin #define PLAT_MAX_PWR_LVL U(3) 60174a1cfeSYidi Lin #define PLAT_MAX_RET_STATE U(1) 61174a1cfeSYidi Lin #define PLAT_MAX_OFF_STATE U(9) 62174a1cfeSYidi Lin 63174a1cfeSYidi Lin #define PLATFORM_SYSTEM_COUNT U(1) 64174a1cfeSYidi Lin #define PLATFORM_MCUSYS_COUNT U(1) 65174a1cfeSYidi Lin #define PLATFORM_CLUSTER_COUNT U(1) 66174a1cfeSYidi Lin #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 67174a1cfeSYidi Lin #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 68174a1cfeSYidi Lin 69174a1cfeSYidi Lin #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 70174a1cfeSYidi Lin #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 71174a1cfeSYidi Lin 72174a1cfeSYidi Lin #define SOC_CHIP_ID U(0x8195) 73174a1cfeSYidi Lin 74174a1cfeSYidi Lin /******************************************************************************* 75174a1cfeSYidi Lin * Platform memory map related constants 76174a1cfeSYidi Lin ******************************************************************************/ 77174a1cfeSYidi Lin #define TZRAM_BASE 0x54600000 78174a1cfeSYidi Lin #define TZRAM_SIZE 0x00030000 79174a1cfeSYidi Lin 80174a1cfeSYidi Lin /******************************************************************************* 81174a1cfeSYidi Lin * BL31 specific defines. 82174a1cfeSYidi Lin ******************************************************************************/ 83174a1cfeSYidi Lin /* 84174a1cfeSYidi Lin * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 85174a1cfeSYidi Lin * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 86174a1cfeSYidi Lin * little space for growth. 87174a1cfeSYidi Lin */ 88174a1cfeSYidi Lin #define BL31_BASE (TZRAM_BASE + 0x1000) 89174a1cfeSYidi Lin #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 90174a1cfeSYidi Lin 91174a1cfeSYidi Lin /******************************************************************************* 92174a1cfeSYidi Lin * Platform specific page table and MMU setup constants 93174a1cfeSYidi Lin ******************************************************************************/ 94174a1cfeSYidi Lin #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 95174a1cfeSYidi Lin #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 96174a1cfeSYidi Lin #define MAX_XLAT_TABLES 16 97174a1cfeSYidi Lin #define MAX_MMAP_REGIONS 16 98174a1cfeSYidi Lin 99174a1cfeSYidi Lin /******************************************************************************* 100174a1cfeSYidi Lin * Declarations and constants to access the mailboxes safely. Each mailbox is 101174a1cfeSYidi Lin * aligned on the biggest cache line size in the platform. This is known only 102174a1cfeSYidi Lin * to the platform as it might have a combination of integrated and external 103174a1cfeSYidi Lin * caches. Such alignment ensures that two maiboxes do not sit on the same cache 104174a1cfeSYidi Lin * line at any cache level. They could belong to different cpus/clusters & 105174a1cfeSYidi Lin * get written while being protected by different locks causing corruption of 106174a1cfeSYidi Lin * a valid mailbox address. 107174a1cfeSYidi Lin ******************************************************************************/ 108174a1cfeSYidi Lin #define CACHE_WRITEBACK_SHIFT 6 109174a1cfeSYidi Lin #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 110174a1cfeSYidi Lin #endif /* PLATFORM_DEF_H */ 111